160 Gb/s Bidirectional Polymer-Waveguide Board-Level Optical Interconnects Using CMOS-Based Transceivers

Doany, F. E.; Schow, Clint L.; Baks, Christian; Kuchta, Daniel M.; Pepeljugoski, P.; Schares, Laurent; Budd, R.; Libsch, F.; Dangel, R.; Horst, F.; Offrein, Bert Jan; Kash, J. A.

doi:10.1109/tadvp.2009.2014877

Cited by 135 publications

(49 citation statements)

References 27 publications

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“…In order to establish the communication between two chips, one should setup bidirectional optical interconnects, which usually are realized by choosing different carrier wavelengths for the forward and backward directions [167][168][169][170]. Bidirectional transmission usually has suffered from its sensitivity to backreflections, which lead to crosstalk between opposing transmitted channels and oscillation in bidirectional amplifiers.…”

Section: Bidirectional Multiplexing Technologymentioning

confidence: 99%

Silicon-based on-chip multiplexing technologies and devices for Peta-bit optical interconnects

2014

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An effective solution to enhance the capacity of an optical-interconnect link is utilizing advanced multiplexing technologies, like wavelength-division-multiplexing (WDM), polarization-division multiplexing (PDM), spatial-division multiplexing (SDM), bi-directional multiplexing, etc. On-chip (de)multiplexers are necessary as key components for realizing these multiplexing systems and they are desired to have small footprints due to the limited physical space for on-chip optical interconnects. As silicon photonics has provided a very attractive platform to build ultrasmall photonic integrated devices with CMOS-compatible processes, in this paper we focus on the discussion of silicon-based (de)multiplexers, including WDM filters, PDM devices, and SDM devices. The demand of devices to realize a hybrid multiplexing technology (combining WDM, PDM and SDM) as well as a bidirectional multiplexing technologies are also discussed to achieve Peta-bit optical interconnects.

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Section: Bidirectional Multiplexing Technologymentioning

confidence: 99%

Silicon-based on-chip multiplexing technologies and devices for Peta-bit optical interconnects

2014

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“…The propagation loss of waveguide is 0.17 dB every 1 millimeter [39]. On both side of the core-to-core traversal path, on-chip VCSELs and photo-detectors are coupled with waveguide, and each coupler attenuates signal by 1.35 dB [40]. Fig.…”

Section: Power Loss and Propagation Delaymentioning

confidence: 99%

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors

Wang

et al. 2014

IEEE Trans. Comput.

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Abstract-Chip multiprocessor (CMP) is becoming increasingly popular in the processor industry. Efficient network-on-chip (NoC) that has similar performance to the processor cores is important in CMP design. Fat-tree based on-chip network has many advantages over traditional mesh or torus based networks in terms of throughput, power efficiency and latency. It has a bright future in the development of CMP. However, the floorplan design of the fat-tree based NoC is very challenging because of the complexity of topology. There are a large number of crossings and long interconnects, which cause severe performance degradation in the network. In electronic NoCs, the parasitic capacitance and inductance will be significant. In optical ones, large crosstalk noise and power loss will be introduced. The novel contribution of this paper is to propose a method to optimize the fat-tree floorplan, which can effectively reduce the number of crossings and minimize the interconnect length. Two types of floorplans are proposed, which could be applied to fat-tree based networks of arbitrary size. Compared with the traditional one, our floorplans could reduce more than 87% of the crossings. Since the traversal distance for signals is related to the aspect ratio of the processor cores, we also present a method to calculate the optimum aspect ratio of the processor cores to minimize the traversal distance.

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“…Even with a less aggressive use of optics, one should at least expect that optics will support most of the off-chip communications, including on-card links [11] between processors and processor-to-memory links [12]. This increased use of optics can only occur if the cost and power of an optical link can be substantially…”

Section: Projections For Future Supercomputersmentioning

confidence: 99%

“…Their bulk becomes also becomes an issue as the cable count increases. Replacing the fibers with polymer waveguides on the printed circuit board [11,16] can eliminate much of the manual assembly, fiber count and cost, just as the introduction of printed circuit boards did for electrical wiring. The chip-like transceivers for these links have already demonstrated power as low as 5pJ/bit [17].…”

Section: Optical Technologies For the Exascalementioning

confidence: 99%

Optical Interconnects in Future Servers

Kash

Benner²,

Doany

et al. 2011

Optical Fiber Communication Conference/National Fiber Optic Engineers Conference 2011

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Optical interconnects are common in today's petascale supercomputers, and will become pervasive at the exascale during this decade. Technologies that can meet the challenging technological and economic requirements for the exascale will be reviewed. Optics in Petascale SupercomputersIn 2008, Roadrunner[1], the first petaflop supercomputer (i.e., >10 15 floating point operations per second) was constructed. The large number of microprocessor cores in such petascale machines must be interconnected with a high capacity communications network to permit efficient computation. Higher interconnect bandwidth will generally result in more efficient use of the microprocessors in real calculations. Prior to 2005, this network used electrical interconnects in essentially all supercomputers. Communication bitrates increased beyond ~2Gb/s starting in about 2005. For distances greater than about 20m, electrical interconnects were impractical and optics began to be used for these longer rack-to-rack interconnects (e.g., ASCI Purple[2]). For cost reasons, however, the shorter rack-to-rack interconnect in this machine was still electrical. By 2008, communication bitrates had increased to 5Gb/s (InfiniBand DDR), and the practical reach of electrical interconnects was shorter. At the same time, the cost of optics had decreased. As a result, for Roadrunner, all node-to-node communication was optical. However, in these examples, all the intra-node communication was electrical. Also, the conversion to optics was at the edge of the node/rack, requiring an electrical interconnect from the chip through several levels of packaging before conversion to photons. For machines with peak performance beyond 10PF, optics will play a far more important role. For example, in the planned POWER7-IH systems [3], all the board-to-board interconnects, will be optical. A major change in the packaging tightly integrates the optics onto the chip-level package. Optical transmitter and receiver modules are placed on the same ceramic Hub (switch) Module [4,5] , with each channel using a 10Gb/s signaling rate and 8b10b coding. Projections for future supercomputersBecause microprocessor clock speeds are not rapidly increasing, supercomputing performance improvements come from larger numbers of processing cores operating in parallel. For example [7], the #1 machine on the top500 list from June, 2002 was the NEC Earth-Simulator with 5120 single core processor chips, as compared to Roadrunner which has some 97,920 cores in 12,240 Cell Broadband Engine® processor chips plus 6,562 dual-core AMD Opteron® chips [8]. This increasing core and chip count drives increasing communication bandwidth at higher bitrates.Trends for optical interconnects in future supercomputers can be extrapolated from past growth. Historically, computational power has grown approximately 10x every 4 years [7], and this growth is expected to continue. Affordable supercomputing requires that the cost and power consumption of supercomputers grow more slowly than computational power. ...

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160 Gb/s Bidirectional Polymer-Waveguide Board-Level Optical Interconnects Using CMOS-Based Transceivers

Cited by 135 publications

References 27 publications

Silicon-based on-chip multiplexing technologies and devices for Peta-bit optical interconnects

Silicon-based on-chip multiplexing technologies and devices for Peta-bit optical interconnects

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors

Optical Interconnects in Future Servers

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