15nm-diameter 3D stacked nanowires with independent gates operation: &amp;#x03A6;FET

Dupré, C.; Hubert, A.; Beçu, S.; Jublot, M.; Maffini-Alvaro, V.; Vizioz, C.; Aussenac, F.; Arvet, C.; Barnola, S.; Hartmann, J.-M.; Garnier, G.; Allain, F.; Colonna, J. P.; Rivoire, M.; Baud, L.; Pauliac, S.; Loup, V.; Chevolleau, T.; Rivallin, P.; Guillaumot, B.; Ghibaudo, G.; Faynot, O.; Ernst, T.; Deleonibus, S.

doi:10.1109/iedm.2008.4796805

Cited by 102 publications

(68 citation statements)

References 7 publications

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“…[1][2][3][4][5][6][7] The future may see the use of threedimensional (3D) MOSFETs, such as vertically stacked SiNW FETs, [8][9][10][11][12] for high device densities. An asymmetric channel structure is expected for the vertically stacked SiNW FETs because of the fabrication processes.…”

mentioning

confidence: 99%

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Sato

Kakushima

Ohmori

et al. 2011

Applied Physics Letters

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This letter reports the electrical characteristics of nonuniform silicon nanowire nFETs with asymmetric source and drain widths. For electrostatic properties, reduced drain-induced barrier lowering (DIBL) is achieved in a device in which the source is wider than the drain. For carrier transport properties, higher values of surface-roughness-limited mobility (l SR ) are obtained in the sample with the wider drain size. Our electrostatic model shows that the concentration of lines of electric force is relaxed near the wider source edge, which results in smaller DIBL. The asymmetric l SR is attributed to the channel surface morphology with (110)-and (100)-faceted surfaces.

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mentioning

confidence: 99%

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Sato

Kakushima

Ohmori

et al. 2011

Applied Physics Letters

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“…Indeed, silicon nanowires (SiNWs) are considered a very promising nanodevice technology for lowpower systems because of their ultimate mono-dimensional semiconductor properties combined with the vast experience and investment in Si technologies. Fabrication technologies for SiNW have been the object of recent investigation through bottom-up [ Yu and Lieber 2010;Heinzig et al 2011;Yan et al 2011] and top-down [Dupré et al 2008;Bera et al 2006] approaches.…”

Section: Low-power High-performances Devices: Towards Thin Devicesmentioning

confidence: 99%

A Survey on Low-Power Techniques with Emerging Technologies

Gaillardon

Beigné

Lesecq

et al. 2015

J. Emerg. Technol. Comput. Syst.

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Nowadays, power consumption is one of the main limitations of electronic systems. In this context, novel and emerging devices provide new opportunities to extend the trend toward low-power design. In this survey article, we present a transversal survey on energy-efficient techniques ranging from devices to architectures. The actual trends of device research, with fully depleted planar devices, tri-gate geometries, and gateall-around structures, allows us to reach an increasingly higher level of performance while reducing the associated power. In addition, beyond the simple device property enhancements, emerging devices also lead to innovations at the circuit and architectural levels. In particular, devices whose properties can be tuned through additional terminals enable a fine and dynamic control of device threshold. They also enable designers to realize logic gates and to implement power-related techniques in a compact way unreachable to standard technologies. These innovations reduce power consumption at the gate level and unlock new means of actuation in architectural solutions like adaptive voltage and frequency scaling.

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“…Thus, for a given value of silicon thickness and oxide (t si =10 nm and t ox =1.5 nm) the corresponding minimum length for the bulk, thin BOX FDSOI, and nanowire are 20 nm, 15 nm and 10 nm respectively. That is why ITRS recommends nanowires for technology node sub-22nm (International (Dupre & al., 2008), twin (Hwi Cho & al., 2007) or single Ω-FET nanowires (Tachi & al., 2009). In the following, a complete study of the electrostatics of nanowire MOSFETs is performed including all the ultimate physical phenomena which can occur in future electronic devices.…”

Section: Fig 1 A) Different Mosfet Architectures Observed By Tem (Fmentioning

confidence: 99%

“…Insulator FDSOI (Barral & al., 2007a), Double Gate (Barral & al., 2007b), finFET (Dupre & al., 2008) and stacked nanowires (Dupre & al., 2008)); b) schematics of the downscaling concept.…”

Section: Fig 1 A) Different Mosfet Architectures Observed By Tem (Fmentioning

confidence: 99%

Nanowires: Promising Candidates for Electrostatic Control in Future Nanoelectronic Devices

Dura¹,

Martinie²,

Munteanu³

et al. 2012

Electrostatics

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15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

Cited by 102 publications

References 7 publications

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

A Survey on Low-Power Techniques with Emerging Technologies

Nanowires: Promising Candidates for Electrostatic Control in Future Nanoelectronic Devices

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