14.6 A scalable THz 2D phased array with &amp;#x002B;17dBm of EIRP at 338GHz in 65nm bulk CMOS

Tousi, Yahya; Afshari, Ehsan

doi:10.1109/isscc.2014.6757425

Cited by 69 publications

(21 citation statements)

References 2 publications

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“…To lock the still at , the phase of output voltage needs to be shifted to create and inject another imaginary current component into the tank to compensate for . According to (3), when there is a phase shift between and , the imaginary current component can be expressed as (5) where is the input/output voltage amplitude. By equalizing and , we can get the expression for the phase shift , (6) According to (6), tuning shifts the output phase by , and thus the PLL output phase by .…”

Section: B With Embedded Phase Shiftermentioning

confidence: 99%

“…A GRESSIVE scaling of CMOS technology has made millimeter-wave (mm-Wave) applications in CMOS become feasible and attractive, such as 60-GHz WiGi/802.11ad [1], 77-GHz vehicle radar [2], 94-GHz imaging radar/sensor [3], [4] and terahertz imaging and spectroscopy [5]. The phase-locked loop (PLL) is a critical sub-system used in these mm-Wave transceivers (TRXs) to generate a local oscillator (LO) signal for frequency conversion or as a signal source for radiation.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Analysis and Design of a 14.1-mW 50/100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS

Yue

Luong

Hong

2015

IEEE Trans. Microwave Theory Techn.

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A low-voltage and low-power 50/100-GHz transformer-based phase-locked loop (PLL) is implemented in a 65-nm CMOS technology. Consuming only 14.1 mW from a 0.6/1.2-V supply, the PLL measures phase noise of 90/ 84 dBc/Hz at 100-kHz offset and 94/ 88 dBc/Hz at 1-MHz offset at 49.7/99.4 GHz while occupying a core chip area of 0.39 mm . Moreover, with an embedded phase shifter, the PLL output phase can be shifted by a 360 range with an average resolution of 3.9 and amplitude variation less than 0.1 dB, which makes it suitable for phased-array transceivers. Index Terms-CMOS, frequency divider, millimeter-wave (mm-Wave), phase-locked loop (PLL), phase shifter, phased array, voltage-controlled oscillator (VCO).

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Section: B With Embedded Phase Shiftermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis and Design of a 14.1-mW 50/100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS

Yue

Luong

Hong

2015

IEEE Trans. Microwave Theory Techn.

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“…In [5], a 4 × 4 phased array is reported capable of generating the radiated power as high as 0.8 mW, with the peak EIRP (equivalent isotropically radiated power) of +17.1 dBm (51 mW) at 338 GHz. The process used is 65 nm bulk CMOS.…”

Section: Oscillators Coupled By Phase Shifter For Power Combinationmentioning

confidence: 99%

Towards solid-state realization of THz signal generation

Zhang

2014

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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The state-of-the-art in solid-state generation of radio frequency ranging from 300 GHz to 3 THz (named as THz signal in this article) is reviewed. Three types of signal sources are covered: oscillators in conventional ICs made of CMOS, SiGe-HBTs, and III-V HEMTs; photo-mixing (also called optical heterodyning); and use of channel plasma-wave instability in 2DEG (2-dimensional electron gas) devices. All those electronic generations can also be categorized as transit-time limited or not. We will describe in some more details the operation principles and mathematical formulation for the plasmawave generated THz emission. Finally, the exploration of new nanomaterials such as graphene for the purpose of THz generation is mentioned.

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“…However, it's difficult to get a low phase noise, high stability, and high power signal source at millimeter-waves frequencies. In general, Nth harmonic oscillators [1][2] and Amplifier Multiplier Chains (AMC) [3][4] are the two most commonly used methods. In AMC, a power amplifier is employed to amplify the signal generated by a low and stable frequency signal source, then the amplified signal is multiplied to high frequency by multiplier.…”

Section: Introductionmentioning

confidence: 99%

An amplifier-doubler chain with conversion gain improvement techniques

Zhang

et al. 2018

IEICE Electron. Express

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This paper presents an amplifier-douler chain to double the signal frequency from 21GHz to 42GHz with about 10GHz bandwidth of output frequency. For the improvement of conversion gain, the doubler adopts the fully differential Gilbert structure which provides large bandwidth and high conversion gain. Meanwhile, an inductive series LC network is used to form resonant tank with the parasitic capacitor to suppress the second harmonic of input frequency, hence the conversion gain of doubler is improved. Once again, the RLC parallel resonant network is employed as load of doubler and power amplifier, and it can improve bandwidth and conversion gain, too. What's more, transformer matching networks (TMN) are adopted to optimize the bandwidth and conversion gain of amplifier-douler chain. Finally, the amplifier-douler chain which fabricated by IBM SiGe 0.13μm BiCMOS technology shows 6.1dB conversion gain and -4.1dBm saturation output power with 26.5mA operating current and 2.8V supply voltage, and the fundamental and 3 rd harmonic rejection at 42GHz are 17.5dB and 38.6dB, respectively.

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14.6 A scalable THz 2D phased array with +17dBm of EIRP at 338GHz in 65nm bulk CMOS

Cited by 69 publications

References 2 publications

Analysis and Design of a 14.1-mW 50/100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS

Analysis and Design of a 14.1-mW 50/100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS

Towards solid-state realization of THz signal generation

An amplifier-doubler chain with conversion gain improvement techniques

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