13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference

Chih, Yu-Der; Shih, Yu-Jen; Lee, Chia-Fu; Chang, Yu-Hao; Lee, Po-Hao; Lin, Hon-Jarn; Chen, Yulin; Lo, Chieh-Pu; Shih, Meng-Chun; Shen, Kuei-Hung; Chuang, Harry; Chang, Tsung-Yung Jonathan

doi:10.1109/isscc19947.2020.9062955

Cited by 71 publications

(16 citation statements)

References 3 publications

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“…Furthermore, an energy efficiency improvement of 40%-70% was achieved via its parallel in-memory delay computations. [94] (of approximately 1 µA/MHz/b). Embedded STT-MRAMs with a capacity of up to 1 Gb were fabricated for industrial MCU/IoT applications based on a 28-nm FDSOI process, and endurance of 10 10 was reported [95][96][97].…”

Section: Energy Efficiency Challengementioning

confidence: 99%

A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

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In traditional von Neumann computing architectures, the essential transfer of data between the processor and memory hierarchies limits the computational efficiency of next-generation system-on-a-chip. The emerging in-memory computing (IMC) approach addresses this issue and facilitates the movement of significant data and rapid computations. Among the different memory types, intrinsic energy efficiency is demonstrated by in-magnetic random access memory (MRAM) computing with a low-power spintronic magnetic tunnel junction device and hybrid integration at an advanced complementary metal-oxide semiconductor node. This study reviews state-of-the-art techniques for managing IMC with an emphasis on spin-transfer torque-MRAM computing via design schemes at the bit-cell, circuit, and system levels. In addition, this study presents effective design techniques and potential challenges and demonstrates the existing limitations of in-MRAM computing and potential methods for overcoming these issues. This study also considers the design technology co-optimization from the IMC perspective.

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Section: Energy Efficiency Challengementioning

confidence: 99%

A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

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“…2) Optimizing Read/Write Latency and Energy at Target WER and RD: Recent state-of-the-art STT-MRAMs can compete or outperform SRAMs in all aspects except write energy and write latency [6], [13], [14]. However, for AI accelerator applications, by scaling ∆ and the retention time of STT-MRAM we can circumvent the write energy and latency limitations.…”

Section: Optimizing Stt-mram For Ai Acceleratorsmentioning

confidence: 99%

“…We can exploit this relationship to reduce the write latency with scaling down of ∆. From Equation (14) we infer that retention time t ret is exponentially proportional to ∆. Thus, depending on the desired retention period of STT-MRAM in AI accelerator, we can optimally scale down ∆, and also minimize write latency at that target retention time.…”

Section: Optimizing Stt-mram For Ai Acceleratorsmentioning

confidence: 99%

Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM

Mishty

Sadi

2021

IEEE Trans. VLSI Syst.

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In this paper, we demonstrate the design of efficient and high-performance AI/Deep Learning accelerators with customized STT-MRAM and a reconfigurable core. Based on modeldriven detailed design space exploration, we present the design methodology of an innovative scratchpad-assisted on-chip STT-MRAM based buffer system for high-performance accelerators. Using analytically derived expression of memory occupancy time of AI model weights and activation maps, the volatility of STT-MRAM is adjusted with process and temperature variation aware scaling of thermal stability factor to optimize the retention time, energy, read/write latency, and area of STT-MRAM. From the analysis of modern AI workloads and accelerator implementation in 14nm technology, we verify the efficacy of our designed AI accelerator with STT-MRAM (STT-AI). Compared to an SRAMbased implementation, the STT-AI accelerator achieves 75% area and 3% power savings at iso-accuracy. Furthermore, with a relaxed bit error rate and negligible AI accuracy trade-off, the designed STT-AI Ultra accelerator achieves 75.4%, and 3.5% savings in area and power, respectively over regular SRAM-based accelerators.

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“…Figure 1 summarizes device and circuit conference publications relating to eNVMs from 2016 to 2020 [3,4,5,6,7,8,10,12,13,14,16,18,19,22,23,24,25,27,28,29,30,31,32,34,35,36,39,41,42,43,44,45,46,47,48,49,50,51,52,53,54,57,58,59,60,61,62,64,65,66,67,68,…”

Section: Introductionmentioning

confidence: 99%

NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories

Pentecost¹,

Hankin²,

Donato³

et al. 2021

Preprint

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Repeated off-chip memory access to DRAM drive up operating power for data-intensive applications, and SRAM technology scaling and leakage power limits the efficiency of embedded memories. Future on-chip storage will need higher density and energy efficiency, and the actively expanding field of emerging, embeddable non-volatile memory (eNVM) technologies is providing many potential candidates to satisfy this need. Each technology proposal presents distinct trade-offs in terms of density, read, write, and reliability characteristics, and we present a comprehensive framework for navigating and quantifying these design trade-offs alongside realistic system constraints and application-level impacts. This work evaluates eNVM-based storage for a range of application and system contexts including machine learning on the edge, graph analytics, and general purpose cache hierarchy, in addition to describing a freely available (http://nvmexplorer.seas.harvard.edu/) set of tools for application experts, system designers, and device experts to better understand, compare, and quantify the next generation of embedded memory solutions.

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13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference

Cited by 71 publications

References 3 publications

A survey of in-spin transfer torque MRAM computing

A survey of in-spin transfer torque MRAM computing

Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM

NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories

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