12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V&lt;inf&gt;MIN&lt;/inf&gt; applications

Chang, Jonathan; Chen, Yen-Huei; Chan, Wei-Min; Preet, Singh; Cheng, Hu; Fujiwara, Haruhiko; Jih-Yu, Lin; Kao-Cheng, Lin; John, Hung; Lee, Robin; Liao, Haijun; Liaw, Jhon-Jhy; Li, Quincy; Lin, Cai; Chiang, Mu-Chi; Wu, Shien-Yang

doi:10.1109/isscc.2017.7870333

Cited by 47 publications

(33 citation statements)

References 2 publications

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“…The standard deviation of V TH in 45 nm CMOS process node reaches approximately 16 % of the mean value [10]. Other affected electrical parameters include parasitics of the chip interconnects, namely parasitic impedance and parasitic capacitance [11]. The characteristics of semiconductor structure alter with time, so electrical parameters of ICs are also affected by ageing.…”

Section: Robustness To Pvt Fluctuationsmentioning

confidence: 99%

Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples

Stopjaková¹,

Rakús²,

Kovac³

et al. 2018

RADIOENGINEERING

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The paper brings an overview of main challenges and design techniques effectively applicable for ultra-low voltage analog integrated circuits in nanoscale technologies. New design challenges linked with a low value of the supply voltage and the process fluctuation in nanotechnologies, such as device models, robustness to process variation, device mismatch and others are discussed firstly. Then, design techniques and approaches to analog integrated circuits towards (ultra) low-voltage systems and applications are described. Finally, examples of basic building blocks of ultra-low voltage analog ICs designed in standard CMOS technology using such design techniques are presented. Finally, the developed circuits are compared to the state-of-the-art solutions in terms of the main parameters and features.

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Section: Robustness To Pvt Fluctuationsmentioning

confidence: 99%

Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples

Stopjaková¹,

Rakús²,

Kovac³

et al. 2018

RADIOENGINEERING

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“…However, the development of eNVMs remains at 22nm [6] or 40nm [7] thus lags behind the logic transistor scaling. Instead, SRAM is a mature embedded memory technology that is available at 7nm and beyond [8]. SRAM-CIM at 7nm provides higher density than 28nm RRAM-CIM (even with 4-bit per cell) [9].…”

Section: Introductionmentioning

confidence: 99%

Xor-Cim

Huang

Jiang

Peng

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…The standard deviation of the transistor threshold voltage (V T H ) in 45 nm CMOS process node reaches approximately 16% of the mean value [2]. Other affected electrical parameters include parasitics of the chip interconnects, namely parasitic impedance and parasitic capacitance [3].…”

Section: Introductionmentioning

confidence: 99%

Digital Calibration of Operational Amplifiers and Influence of Calibration Circuitry

SovSik

Stopjaková

Arbet

et al. 2018

2018 International Conference on Applied Electronics (AE)

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This paper presents the implementation of a digital calibration method for a variable-gain amplifier (VGA), where the amplifier input offset voltage is the calibration target. The whole system is implemented in 130 nm CMOS technology using the supply voltage of 600 mV . Firstly, fundamentals of calibration circuitry operation are described, followed by detailed explanation of the proposed implementation. Then, investigation of possible undesired effects of calibration circuitry on the amplifier characteristics is performed. The whole calibration system was verified through simulation for various temperatures using Cadence environment and BSIM3v3 transistor model version. The VGA was calibrated within the temperature range from −20 • C to 60 • C, in which standard deviation of the input offset voltage reaches less than 802 µV and mean value is at most 450 µV . Using the calibration, the standard deviation is reduced to 35% compared to the VGA without the calibration, while the change of mean value is rather negligible.

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12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V<inf>MIN</inf> applications

Cited by 47 publications

References 2 publications

Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples

Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples

Xor-Cim

Digital Calibration of Operational Amplifiers and Influence of Calibration Circuitry

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