112 Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process

Krupnik, Yoel; Perelman, Yevgeny; Levin, Itamar; Sanhedrai, Yosi; Eitan, Roee; Khairi, Ahmad; Landau, Yoni; Virobnik, Udi; Dolev, Noam; Meisler, Alon; Cohen, Ariel

doi:10.23919/vlsic.2019.8778136

Cited by 22 publications

(6 citation statements)

References 4 publications

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“…Recently there have been alternative bootstrapped switch topologies proposed that improve upon the original implementation [15]. One implementation adds two additional PMOS devices and modifies the gate connection to the NMOS charging the boosting capacitor to improve the transition times of the main switch gate [16]. However, one of these additional PMOS devices is directly connected to the input and adds additional loading.…”

Section: B Interleaver Designmentioning

confidence: 99%

A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET

Zhu

Liu

Kaile

et al. 2023

IEEE J. Solid-State Circuits

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Efficient time-interleavedanalog-to-digital converters (ADCs) that operate at high sample rates with wide input bandwidths are necessary to support increasing wireline transceiver data rates. This paper presents a 7-bit 38GS/s 32-way time-interleaved ADC that utilizes an 8-way interleaver architecture based on a speed-enhanced bootstrapped switch that increases input bandwidth. ADC sample rate and efficiency is improved with pipelined successive approximation register (SAR) unit ADCs that employ an output level shifting (OLS) settling technique in the dynamic residue amplifier to achieve settling in only 33% of the time required for a conventional current-mode logic (CML) amplifier. Using parallel comparators in the two 4-bit asynchronous pipeline stages allows for further improvements in ADC conversion speed. Fabricated in 22nm FinFET, the proposed ADC occupies 0.107mm 2 area. Operating at 38GS/s, the ADC achieves 41.9fJ/conv.-step with low input frequencies, 64.1fJ/conv.-step at Nyquist, and has 20GHz 3dB input bandwidth.

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Section: B Interleaver Designmentioning

confidence: 99%

A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET

Zhu

Liu

Kaile

et al. 2023

IEEE J. Solid-State Circuits

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“…While a TX pre-emphasis equalizer, a CTLE, and a DFE are necessary for error-free communication through a lossy electrical channel, the power consumption of those blocks is significant. For short-reach (SR) and long-reach (LR) channels, the energy efficiencies of 0.8-1.2pJ/b [16] and 3-5pJ/b [22], [23], respectively, are typically reported figures. Lowpower equalization/modulation/coding techniques have been explored to increase bandwidth-energy-efficiency.…”

Section: Wireline Interface Overviewmentioning

confidence: 99%

Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators

Lee

Kim

Park

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In convolutional neural network (CNN) accelerators, the dominant power consumption is caused by the access of external data memory. In addition, power and area occupied by I/O interfaces maintaining low bit-error-rate, e.g., 1e-15, grow as the data rate increases. Considering the inherent error resilience of the inference process in machine learning applications, the requirement of error-free communication in the data-path is controversial. In this paper, a custom CNN accelerator integrating a channel emulator is designed by using an FPGA to analyze the effect of the BER of an I/O transceiver on the image classification accuracy. In order to implement a channel emulator, a digital-domain look-up-table (LUT)-based 12-tap FIR filter is employed to create inter-symbol interference (ISI), and a PRBS31 generator is used as a noise source. The implementation was evaluated by running the ImageNet dataset on the FPGA-based custom accelerator (Virtex Ultrascale+) implementing VGG-16. The results show that the BER up to 1e-4 in the memory access has a negligible impact on the inference accuracy.

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“…This led to a rising interest in high-speed wireline communication systems with ever-increasing data rates, especially in data center applications. As of now, the most employed modulation in SerDes transceivers is Pulse Amplitude Modulation with four levels (PAM-4) [1][2][3], which allows doubling the data rate using the same symbol rate compared to Non-Return-to-Zero (NRZ) modulation. To achieve even higher data rates, the symbol rate of the system can be increased, but this approach is limited by the bandwidth of the channel.…”

Section: Introductionmentioning

confidence: 99%

A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

Pasquo

Monaco²,

Ghittori³

et al. 2022

Electronics

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In this brief, we propose a 60 GS/s high-linearity two-stage 8 × 8 time-interleaved track-and-hold circuit where it is possible to tune the static non-linearities of the second-stage buffer by applying a proper bias voltage. This allows us to maximize the static linearity of the buffer or introduce effects that counterbalance the non-linearities of other blocks of the analog front-end. To validate the proposed circuit, a prototype in TSMC 5 nm technology is designed and a linearity calibration loop is proposed for a Pulse Amplitude Modulation SerDes receiver. For the analog buffer, circuit-level simulations are performed in Cadence Virtuoso, while the calibration loop is simulated in MATLAB. The optimal bias voltage value can be found by modeling the track-and-hold linearity using a Taylor series and implementing the linearity calibration loop in MATLAB. By applying this result to the circuit-level simulation, we obtain a total harmonic distortion of over 50 dB, which matches with the maximum value achievable across the complete bias voltage control range. Lastly, the linearity of the system is also verified using a PAM-8 pseudorandom stream signal.

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112 Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process

Cited by 22 publications

References 4 publications

A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET

A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET

Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators

A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

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