11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13&amp;#x03BC;m CMOS with 74dB SNDR

Chang, Dong-Young; Munoz, Carlos E.; Daly, Denis C.; Shin, Susanna; Guay, Kevin C.; Thurston, Thomas; Lee, Hae-Seung; Gulati, Kush; Straayer, M.Z.

doi:10.1109/isscc.2014.6757401

Cited by 14 publications

(9 citation statements)

References 2 publications

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“…The comparator detects when v O arrives to the correct value because its input voltage crosses zero-at that point in time the sampling switch of the next stage is opened and the comparator is turned off, no longer consuming power. Furthermore, this solution does not suffer from stability and gain-bandwidth product limitations that are typical of negative feedback amplifiers [59]. All this makes it a very power efficient technique.…”

Section: Adcs With Residue Amplificationmentioning

confidence: 99%

“…It is a natural choice in this case, given that in practical SAR ADC implementations the S/H, DAC and subtractor operations are performed by a single switched capacitor circuit. A variation of this architecture is the combination of a flash coarse quantizer with a SAR fine quantizer [59], 8 [60]. The objective is to increase operating speed, with respect to that obtained with just the SAR, since the first few MSBs are determined in a single cycle.…”

Section: Dacmentioning

confidence: 99%

“…Furthermore there is only one comparator whose offset must be made low enough. Reference [59] implements the 7 bit quantizer in its last stage as a two-step subranging ADC composed of a coarse flash ADC and a fine SAR ADC. The 4.5bit quantizers (the meaning of this will be explained shortly) used on the other stages are also two-step subranging converters, but with coarse and fine flash ADCs.…”

Section: Quantizermentioning

confidence: 99%

“…Another solution [84] consists of increasing amplifier current during the initial part of the amplification phase, boosting slew- rate and amplifier bandwidth when it is most needed, and requires almost no extra complexity. Figure 29 depicts a simplified diagram of the comparator based 1.5 bit MDAC [59,90], where the amplifier is substituted by a continuous-time comparator and a current source. The output voltage is set to a value higher than V REF before the amplification phase starts, during which it is discharged by a current source.…”

Section: Adcs With Residue Amplificationmentioning

confidence: 99%

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Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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This chapter discusses the architectures of Nyquist rate Analog-toDigital Converters (ADCs), that are embedded in systems-on-chip (SoCs) implementing some of the most widespread mobile communication, wireless and wireline connectivity standards. The typical requirements for these ADCs are presented, and the main conversion architectures are described in terms of the fundamental operations realized inside them. This constitutes a unified treatment that relates all architectures, thus providing a deeper understanding of their fundamental limitations and trade-offs. We then discuss some of the solutions recently published in the literature to improve ADC energy efficiency. Finally we disclose implementation details from two 12 bit digitally calibrated, high-speed ADCs, using the pipeline and SAR architectures.

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Section: Adcs With Residue Amplificationmentioning

confidence: 99%

Section: Dacmentioning

confidence: 99%

Section: Quantizermentioning

confidence: 99%

Section: Adcs With Residue Amplificationmentioning

confidence: 99%

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Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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“…Several alternative approaches have been proposed to overcome the problems of conventional OTA-based SC circuits, including inverter-based SC circuits [1], [2], and zero-crossing based circuits [3]- [7]. Inverter based SC circuits have limited accuracy due to the limited gain of a single inverter.…”

Section: Introductionmentioning

confidence: 99%

A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers

Lim

Flynn

2015

IEEE J. Solid-State Circuits

109

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The ring amplifier is an energy efficient and high output swing alternative to an OTA for switched-capacitor circuits. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. This paper presents a self-biased ring amplifier scheme that makes the ring amplifier more practical and power efficient while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. We introduce an improved auto-zero scheme that eliminates the gain error caused by the parasitic capacitance across the auto-zero switch. Furthermore, a comparator-less pipeline ADC structure takes advantage of the characteristics of the ring-amplifier to replace the sub-ADC in each pipeline stage. The prototype ADC has measured SNDR, SNR and SFDR of 56.6 dB (9.11 b), 57.5 dB and 64.7 dB, respectively, for a Nyquist frequency input sampled at 100 MS/s, and consumes 2.46 mW.Index Terms-A/D, ADC, analog to digital converter, auto-zero, comparator-less ADC, energy efficient, low power, ring amplifier, self-biased ring amplifier, switched capacitor.

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