11.1 A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET Technology

Yousry, Ramy; Chen, E-Hung; Ying, Yu-Ming; Abdul-Latif, Mohammed; Elbadry, Mohammad; ElShater, Ahmed; Liu, Tsz-Bin; Lee, Joonyeong; Ramachandran, Dhinessh; Wang, Kaiz; Weng, Chih-Hao; Wu, Mau-Lin; Ali, Tamer

doi:10.1109/isscc42613.2021.9365752

Cited by 25 publications

(11 citation statements)

References 5 publications

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“…Data rates reached 2.5 Gbps in the middle of the 1990s, as reported in [14]. Nowadays, they exceed one hundred Gbps at a single lane, and tens of Tbps of aggregate bandwidth is achieved for many-lanes short-range interfaces [25]. To achieve such a high bandwidth, designers rely on advanced equalization techniques [15], [18], [24], [25] to compensate the signal attenuation on the channel at extremely high frequencies, as well as PAM4 [24], [25] which utilizes four voltage levels for signaling on its physical layer, in addition to extremely aggressive technology scaling.…”

Section: Related Workmentioning

confidence: 88%

“…High-speed serial interfaces have been extensively studied over the last decades [14]- [21], [23]- [25]. Data rates reached 2.5 Gbps in the middle of the 1990s, as reported in [14].…”

Section: Related Workmentioning

confidence: 99%

“…Nowadays, they exceed one hundred Gbps at a single lane, and tens of Tbps of aggregate bandwidth is achieved for many-lanes short-range interfaces [25]. To achieve such a high bandwidth, designers rely on advanced equalization techniques [15], [18], [24], [25] to compensate the signal attenuation on the channel at extremely high frequencies, as well as PAM4 [24], [25] which utilizes four voltage levels for signaling on its physical layer, in addition to extremely aggressive technology scaling. The equalization techniques are essential, especially when serial interfaces are designed for lossy channels (e.g., long channel applications), which deteriorate the transmitted signal quality.…”

Section: Related Workmentioning

confidence: 99%

“…While the other links achieve higher bandwidth and energy-efficiency than ours, they are missing the option to be integrated into actual microcontrollers. Indeed, the works from [23], [25], [27] are not suitable for low power applications as their total power consumption is much higher than the power envelope of an IoT edge devices (10mW). Also, the work in [21] does not consider power overhead imposed by extra voltage sources.…”

Section: Comparison To Other Short Reach Linksmentioning

confidence: 99%

“…They utilize low-voltage swing signals at the physical layer, which enable data communications at a higher-rate and lower-power consumption than the existing digital interface. Indeed, pursuing the maximum bandwidth has been the key metric driving link design, and state-of-the-art links achieve tens or even hundreds of Gbps for high-performance applications [23]- [25]. In domains like the HPC, serial interfaces have already become an essential building block [11].…”

Section: Introductionmentioning

confidence: 99%

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A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

Okuhara

Elnaqib

Dazzi

et al. 2021

IEEE Trans. VLSI Syst.

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The increasing complexity of Internet-of-Things (IoT) applications and near-sensor processing algorithms is pushing the computational power of low-power, battery-operated endnode systems. This trend also reveals growing demands for highspeed and energy-efficient inter-chip communications to manage the increasing amount of data coming from off-chip sensors and memories. While traditional micro-controller interfaces such as SPIs cannot cope with tight energy and large bandwidth requirements, low-voltage swing transceivers can tackle this challenge thanks to their capability to achieve several Gbps of the communication speed at milliwatt power levels. However, recent research on high-speed serial links focused on high-performance systems, with a power consumption significantly larger than the one of low-power IoT end-nodes, or on stand-alone designs not integrated at a system level. This paper presents a low-swing transceiver for the energy-efficient and low power chip-to-chip communication fully integrated within an IoT end-node Systemon-Chip, fabricated in CMOS 65nm technology. The transceiver can be easily controlled via a software interface; thus, we can consider realistic scenarios for the data communication, which cannot be assessed in stand-alone prototypes. Chip measurements show that the transceiver achieves 8.46x higher energy efficiency at 15.9x higher performance than a traditional microcontroller interface such as a single-SPI.

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Section: Related Workmentioning

confidence: 88%

“…High-speed serial interfaces have been extensively studied over the last decades [14]- [21], [23]- [25]. Data rates reached 2.5 Gbps in the middle of the 1990s, as reported in [14].…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Comparison To Other Short Reach Linksmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

Okuhara

Elnaqib

Dazzi

et al. 2021

IEEE Trans. VLSI Syst.

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Design Methods of Integrated Circuits, Working Under Non-standard Operating Conditions

Melikyan

2023

Machine Learning-Based Design and Optimization of High-Speed Circuits

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Co-packaged optics (CPO): status, challenges, and solutions

Tan

Liu³

et al. 2023

Front. Optoelectron.

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Due to the rise of 5G, IoT, AI, and high-performance computing applications, datacenter traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three-fourths of the datacenter traffic resides within datacenters. The conventional pluggable optics increases at a much slower rate than that of datacenter traffic. The gap between application requirements and the capability of conventional pluggable optics keeps increasing, a trend that is unsustainable. Co-packaged optics (CPO) is a disruptive approach to increasing the interconnecting bandwidth density and energy efficiency by dramatically shortening the electrical link length through advanced packaging and co-optimization of electronics and photonics. CPO is widely regarded as a promising solution for future datacenter interconnections, and silicon platform is the most promising platform for large-scale integration. Leading international companies (e.g., Intel, Broadcom and IBM) have heavily investigated in CPO technology, an inter-disciplinary research field that involves photonic devices, integrated circuits design, packaging, photonic device modeling, electronic-photonic co-simulation, applications, and standardization. This review aims to provide the readers a comprehensive overview of the state-of-the-art progress of CPO in silicon platform, identify the key challenges, and point out the potential solutions, hoping to encourage collaboration between different research fields to accelerate the development of CPO technology. Graphical Abstract

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11.1 A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET Technology

Cited by 25 publications

References 5 publications

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

Design Methods of Integrated Circuits, Working Under Non-standard Operating Conditions

Co-packaged optics (CPO): status, challenges, and solutions

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