2008 IEEE Compound Semiconductor Integrated Circuits Symposium 2008
DOI: 10.1109/csics.2008.36
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100 Gbit/s Fully Integrated InP DHBT-Based CDR/1:2 DEMUX IC

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Cited by 11 publications
(3 citation statements)
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“…High-speed CDR/DEMUX circuits typically consume considerably more energy than MUXs because a larger proportion of the circuit operates at high speed [32]. For example, in [41], a laboratory 100 Gb/s, 1:2 InP HBT-based 1:2 DEMUX consumed 10-30 pJ/b, and in [42], an InP DHBT-based CDR integrated with a 1:2 DEMUX at 100 Gb/s consumed 21 pJ/b. DEMUX circuits with higher demultiplexing ratios (e.g., 1:4, 1:8, and 1:16) consume considerably more energy than a 1:2 DEMUX.…”
Section: E Optical Receiversmentioning
confidence: 99%
“…High-speed CDR/DEMUX circuits typically consume considerably more energy than MUXs because a larger proportion of the circuit operates at high speed [32]. For example, in [41], a laboratory 100 Gb/s, 1:2 InP HBT-based 1:2 DEMUX consumed 10-30 pJ/b, and in [42], an InP DHBT-based CDR integrated with a 1:2 DEMUX at 100 Gb/s consumed 21 pJ/b. DEMUX circuits with higher demultiplexing ratios (e.g., 1:4, 1:8, and 1:16) consume considerably more energy than a 1:2 DEMUX.…”
Section: E Optical Receiversmentioning
confidence: 99%
“…For highest operation speed, the data latches included in the D-FFs are realised using emitter-coupling logic (ECL) as well as series-gating circuit techniques. Furthermore, inductive peaking is applied in association with the resistive load terminating the ECL data input and output of the latches as well as the corresponding ECL clock input [5]. Not least, a relatively low switching voltage level of 200 mV further supports the high-speed operation ability of the DEMUX core.…”
mentioning
confidence: 99%
“…Furthermore, the data input buffer is critical for achieving a high input sensitivity. The clock buffer consists of a transadmittance stage with an open-collector configuration, that is, this buffer device works on the clock input terminations of the four latches included in the DEMUX core [5]. This ensures high-speed driving of the clock input signal to the corresponding inputs of the DEMUX core as well as the elimination of oscillation tendencies on the clock distribution path.…”
mentioning
confidence: 99%