1-Gword/s pseudorandom word generator

McFarland, W.; Springer, K.; Yen, C.-S.

doi:10.1109/4.32036

Cited by 13 publications

(2 citation statements)

References 6 publications

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“…The PRBS source generates , , or patterns matched to our laboratory test equipment and outputs them as two interleaved half-rate 5-Gbps streams [24], [25]. When "load" is asserted, the shift registers accept an external input, which allows the circuit to also act as a PRBS checker: preloading the shift register with a received PRBS data stream will synchronize the circuit to it, so that when "load" is deasserted, the shift register output should match the next received bit exactly [26].…”

Section: Prototype Overviewmentioning

confidence: 99%

10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS

Liu

Patil

Lexau

et al. 2012

IEEE J. Solid-State Circuits

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We describe transmitter and receiver circuits for a 10-Gbps single-ended optical link in a 40-nm CMOS technology. The circuits are bonded using low-parasitic micro-solder bumps to silicon photonic devices on a 130-nm SOI platform. The transmitter drives oval resonant ring modulators with a 2-V swing and employs static thermal tuners to compensate for optical device process variations. The receiver is based on a transimpedance amplifier (TIA) with 4-k gain and designed for an input power of 15 dBm, a photodiode responsivity of 0.7 A/W, and an input extinction ratio of 6 dB. It employs a pair of interleaved clocked sense-amplifiers for voltage slicing and uses a DLL with phase adjustment for centering the clock in the data eye. Periodic calibration allows for adjustment of both voltage and timing margins. At 10 Gbps, the transmitter extinction ratio exceeds 7 dB and, excluding thermal tuning and laser power, it consumes 1.35 mW. At the same datarate, the receiver consumes 3.95 mW. On-chip PRBS generators and checkers with sequences confirm operation at a BER better than .

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Section: Prototype Overviewmentioning

confidence: 99%

10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS

Liu

Patil

Lexau

et al. 2012

IEEE J. Solid-State Circuits

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“…The flip-flops are connected as a parallel register with the output fed back to the input through the XOR gates. The XOR gates are connected so each bit of the new word is generated according to a given polynomial equation[7]. In this paper, we have used 4-to-I multiplexer to form a single high-speed bit stream using the low-speed parallel data generated by 4-bit parallel pattem generators.…”

mentioning

confidence: 99%

45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]

Kim

Kapur

Meghelli

et al.

Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.

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A 2'-l pseudorandom bit sequence (PRBS) generator chip set that operates up to 45Gh/s was fabricated and tested. The circuits are implemented using bipolar transistors in a SiGe BiCMOS technology and operate from a single -3.3V power supply. The PRBS generator, which consumes 1.32W, uses a high speed 4:l multiplexer to produce the final output from four quarter-rate streams. The automatic synchronizing PRBS checker consumes 1.2W and uses a half-rate architecture, demultiplexing the full-rate data stream to lower rate streams that are checked io parallel.

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