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Wiangtong, Theerayod; Cheung, Peter Y. K.; Luk, Wayne

doi:10.1023/a:1016567828852

Cited by 108 publications

(5 citation statements)

References 26 publications

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“…The TGFF tool is a pseudo random task graph generator, it creates problem instances for use in allocation and scheduling research [34]. In the research field of hardware/software partitioning, the TGFF tool is widely used to generate the task graphs to test the performance of Algorithms [19,35,36]. A task graph represents a set of subtask nodes to be partitioned, each node includes the parameters of software execution time, hardware execution time and hardware area, and there is parameter of communication time between two subtask nodes.…”

Section: Methodsmentioning

confidence: 99%

“…For example, Fong et al used the PSO in feature selection [12], Hashim et al applied the the ABC to optimize the wireless sensor network [13], Dai et al solved the path-planning problem based on the ACO [14], Qin et al solved the vehicle routing problem with the ASFA [15], and in our previous work, we designed a local dimming algorithm based on the SFLA [16]. In the hardware/software partitioning area, some SI algorithms were also applied and achieved good performance [17][18][19]. When applying SI to hardware/software partitioning, there are two metrics of interest: the quality of the obtained solutions and the execution time of the algorithms.…”

Section: Introductionmentioning

confidence: 99%

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Using Improved Brainstorm Optimization Algorithm for Hardware/Software Partitioning

2019

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Today, more and more complex tasks are emerging. To finish these tasks within a reasonable time, using the complex embedded system which has multiple processing units is necessary. Hardware/software partitioning is one of the key technologies in designing complex embedded systems, it is usually taken as an optimization problem and be solved with different optimization methods. Among the optimization methods, swarm intelligent (SI) algorithms are easily applied and have the advantages of strong robustness and excellent global search ability. Due to the high complexity of hardware/software partitioning problems, the SI algorithms are ideal methods to solve the problems. In this paper, a new SI algorithm, called brainstorm optimization (BSO), is applied to hardware/software partitioning. In order to improve the performance of the BSO, we analyzed its optimization process when solving the hardware/software partitioning problem and found the disadvantages in terms of the clustering method and the updating strategy. Then we proposed the improved brainstorm optimization (IBSO) which ameliorated the original clustering method by setting the cluster points and improved the updating strategy by decreasing the number of updated individuals in each iteration. Based on the simulation methods which are usually used to evaluate the performance of the hardware/software partitioning algorithms, we generated eight benchmarks which represent tasks with different scales to test the performance of IBSO, BSO, four original heuristic algorithms and two improved BSO. Simulation results show that the IBSO algorithm can achieve the solutions with the highest quality within the shortest running time among these algorithms.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Using Improved Brainstorm Optimization Algorithm for Hardware/Software Partitioning

2019

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“…The partitioning problems has focused on finding the optimal assignment of function blocks of an application to a selected set of PEs such as microprocessor, DSP, or dedicated hardware IP considering time constraints [4,21], power consumption [22,23], and/or hardware area [6,24,25]. To meet both performance and power consumption constraints, task-level multi-objective partitioning algorithms have been developed using iterative heuristic methods [22,25], a genetic algorithm [23,26], and a simulated annealing method [24].…”

Section: Related Work and Contributionsmentioning

confidence: 99%

“…To meet both performance and power consumption constraints, task-level multi-objective partitioning algorithms have been developed using iterative heuristic methods [22,25], a genetic algorithm [23,26], and a simulated annealing method [24].…”

Section: Related Work and Contributionsmentioning

confidence: 99%

“…arbitration delay, memory access latency, bus-bridge overhead, bus protocol overhead, and so on. Among them, the bus arbitration delay due to simultaneous access requests by multiple PEs makes an accurate performance evaluation difficult without the simulation [25,29]. To overcome this problem, we developed the iterative heuristic for the communication architecture synthesis, where an iteration loop is broken down into the three steps as shown in Fig.…”

Section: Communication Architecture Synthesismentioning

confidence: 99%

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A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification

Lee

Kim

2009

J Sign Process Syst Sign Image Video Technol

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The design space exploration (DSE) problem addressed in this paper is to find out Multi-Processor System-on-Chip architectures for a given multi-task signal processing application aiming to minimize the system cost while satisfying the real-time constraints. It involves the following three sub-problems: selecting processing elements, mapping an application to the processing elements, and determining the communication architecture. The proposed approach consists of two inner design loops: one is a cosynthesis loop that determines the selection of PEs and the mapping of a given application to the PEs, and the other is a communication architecture synthesis loop to find the hierarchical shared bus architecture. We specify an application with a synchronous data flow (SDF) model of computation that has well-matched semantics with the algorithmic function flow in DSP applications. To solve the problem, we need to compare the estimated performance of design points and choose the best ones. The common method of simulation-based performance estimation is too time-consuming to explore the wide design space. Thanks to the analytical properties of the SDF model, the performance estimation can be done without HW/SW cosimulation in both loops. A global feedback from the communication architecture synthesis step to the cosynthesis step forms the proposed DSE framework. We use a real-life application, 4-channel Digital Video Recorder (DVR) that is a multi-task example, as well as randomly generated graphs to show the viability of the proposed approach.

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A Unified Codesign Environment

Wiangtong

Cheung

Luk

New Algorithms, Architectures and Applications for Reconfigurable Computing

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Untitled

Cited by 108 publications

References 26 publications

Using Improved Brainstorm Optimization Algorithm for Hardware/Software Partitioning

Using Improved Brainstorm Optimization Algorithm for Hardware/Software Partitioning

A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification

A Unified Codesign Environment

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