The principle of program control means that the processor core turns to the main memory of the computer for operands or instructions. According to architectural features, operands are stored in data segments, and instructions are stored in code segments of the main memory. The operating system uses both page memory organization and segment memory organization. The page memory organization is always mapped to the segment organization. Due to the cached packet cycles of the processor core, copies of the main memory pages are stored in the internal associative cache memory. The associative cache memory consists of three units: a data unit, a tag unit, and an LRU unit. The data unit stores operands or instructions, the tag unit contains fragments of address information, and the LRU unit contains the logic of policy for replacement of string. The missing event attracts LRU logic to decide for substitution of reliable string in the data unit of associative cache memory. The pseudo-LRU algorithm is a simple and better substitution policy among known substitution policies. Two options for the minimization of the hardware for replacement policy by the pseudo-LRU algorithm in q - directed associative cache memory is implemented. The transition from the trigger structure of the synchronous D-trigger to the trigger structure of the synchronous JK-trigger is carried out reasonably in both options. The first option of minimization is based on the sequence for updating of the by the algorithm pseudo LRU, which allows deleting of the combinational logic for updating bits of LRU unit. The second option of minimization is based on the sequence for changing of the q - index of direction, as the consequence for updating the bits of LRU unit by the algorithm pseudo LRU. It allows additionally reducing the number of memory elements. Both options of the minimization allow improving such characteristics as productivity and reliability of the LRU unit.
The probability indicators of the hits or misses events have conditioned the application of the certain substitution policies in the associative cache and the associative translation look-a-side buffer. The implementation of combined substitution policies can improve cache memory and cache buffer performance in general by the interoperability of algorithms with unidirectional or multidirectional substitution policies with the ability to switch from one policy to another. Adaptation of substitution algorithms is based on the compatibility of algorithms according to several characteristics, such as substitution policy, productivity, and implementation complexity. All listed characteristics are summarized in the corresponding table and they are allowed to create the construction for the so-called compatibility matrix, which allows observing not only pairs of compatible algorithms, but also their triads. The substitution policy of the adaptive algorithms extends as to the associative cache memory as to the associative translation look-a-side buffer of the processor core. In the paper, the automaton model of an adaptive algorithm was built and was created by a pair of compatible algorithms. On the one side, the substitution policy algorithm policy should rely on finding and replacing the least recently used or least frequently used element of the addressed set of the data unit. On the other side, this policy may occur in searching and replacing the most recently used or most frequently used element in the addressed set of a data unit. The automaton model is described by the corresponding discrete functions and structural block diagrams of algorithms. The automaton model was created and algorithmized and was the reason for the synthesis of adaptive algorithm hardware for q – directional associative cache memory and associative translation look-a-side buffer. The synthesis was based on the mathematical apparatus of combinatorial synthesis for determining the enabling conditions for selecting q - directions. The result of the synthesis was the logic model of a selection of q – directions according to an adaptive algorithm with the corresponding hardware solution.
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