The
enhancement of terahertz (THz) radiation is of extreme significance
for the realization of the THz probe and imaging. However, present
THz technologies are far from being enough to realize high-performance
and room-temperature THz sources. Fortunately, topological insulators
(TIs), with spin-momentum-locked Dirac surface states, are expected
to exhibit a high terahertz emission efficiency. In this work, the
novel concept of a Rashba-state-enhanced spintronic THz emitter is
demonstrated on the basis of ferromagnet/heavy metal/topological insulator
(FM/HM/TI) heterostructure. We find that the THz emission intensity
changes as a function of HM interlayer thickness, and a 1.98 times
higher intensity compared to that of FM/TI can be achieved when a
meticulously designed thickness of the HM layer is inserted. The improvement
of terahertz radiation is ascribed to the additive effect of Rashba
splitting and topological surface states at the HM/TI interface. These
results offer new possibilities for realizing spintronic THz emitters
in TI-based magnetic heterostructures.
Physical unclonable function (PUF), a hardware that can extract the differences of the same implementations and provide unique secret keys without the utilization of non-volatile memory, is regarded as a promising security primitive in the near future. Ring Oscillator (RO) PUF is one of its easy silicon implementations, which exploits the frequency difference between a pair of structurally identical ring oscillators. However, a large number of ROs must be constructed if multiple stable output bits are required, which means unacceptable area overhead for lightweight applications. To solve this problem, configurable ROs using multiplexers and different delay units were proposed in previous papers. Unfortunately, most of them take advantage of the specific structure of a certain type of field-programmable gate arrays (FPGAs), thus not cost-saving for application-specific integrated circuit (ASIC). In this paper, we propose a configurable RO using only two hybrid logic gates in each stage for ASIC, which costs less area and power compared with previous proposals. Experiment on 50 FPGAs and one self-designed printed circuit board demonstrates satisfactory uniformity and uniqueness of this novel RO PUF. Furthermore, our proposal is proved to be reliable in a wide variety of environment conditions.
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