This paper proposes a low-voltage power amplifier for the 3.0-5.0 GHz ultra-wideband applications. Based on the classical current-reused technique, it adopts a folded topology to achieve the low-voltage working with acceptable output linearity. Its two-stage amplifying configuration consists of only one NMOS and one PMOS transistors. Implemented in the 0.18 m CMOS technology, it obtains a gain as high as 16 dB with only ±0.5 dB flatness over the full working band, and consumes only 23.2 mW with 0.75mm 2 size under 1.2 V.
To speed up the deterioration of a circuit under test (CUT), an input pattern is needed to maximize its leakage power in the static burn-in process. This paper presents an efficient pattern generation method with ATPG approach. To reduce the effort of precise power calculation, a metric that is linearly related to the leakage power of CUT is proposed. This generation method reuses the test set for stuck-at faults, and it can search for the quasi-optimal target pattern in the collapsed pattern space by the equivalent fault model.
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