Test pattern generation for static burn-in based on equivalent fault model

Abstract

To speed up the deterioration of a circuit under test (CUT), an input pattern is needed to maximize its leakage power in the static burn-in process. This paper presents an efficient pattern generation method with ATPG approach. To reduce the effort of precise power calculation, a metric that is linearly related to the leakage power of CUT is proposed. This generation method reuses the test set for stuck-at faults, and it can search for the quasi-optimal target pattern in the collapsed pattern space by the equivalent fault model.