Testing of mixed-signal SoCs becomes one of the pressing challenges due to enormous test cost including ATE expenses, design for test (DFT) hardware overhead and test application time. Prior researches focus mainly on minimizing test cost for digital SoCs under the constraint of ATE test resources and power consumption. A self-hold analog test wrapper design and pipelined parallel test manner are proposed in this paper to realize both core-level and system-level parallel test for low to mid-frequency analog cores in mixed-signal SoCs.Based on virtual-digitization method, we propose a test wrapper design for analog cores reusing on-chip DAC and ADC. Only digital ATEs are required to reduce the expense on mixed-signal ATEs. To further reduce the DFT hardware overhead, we add self-hold analog test interface (SHATI) on each test input or output port to replace extra DAC or ADC. The proposed SHATI design is shown in Fig.1. OPA1 OPA2 Vin Vout C1 SHATI S1 S3 S2 S4 Fig.1 SHATI designTest stimuli can be held under the constraint of accuracy for a certain period of time with resistor-capacitor (RC) pair. The problem is that the time constant τ keeps the same when voltage is applied or held. It seems to be in a dilemma when test stimulus needs to be applied rapidly but held for long enough time with acceptable accuracy to wait for other simultaneous test stimuli. In the proposed SHATI design, small on τ and large hold τ are both obtained to solve the problem. SHATI is designed essentially with two operational amplifiers OPA1 and OPA2. The output resistance of OPA1 and the input resistance of OPA2 work with C1 to construct on τ and hold τ respectively. Four test modes of SHATI are configured by control signals from test wrapper controller. In single-port mode, S1 and S3 are turned on while S3 and S4 are off. Test stimulus from DAC is directly applied on the test input port. In turn-on mode: S1, S2 and S4 are turned on while S3 is off. Test stimulus is applied to the test input port through SHATI. In self-hold mode: S1 and S4 are all turned on and S2 and S3 are off after test stimulus turns steady during turn-on mode. The test stimulus is held on the test input port. In bypass mode: S1, S3 and S4 are turned off. The SHATI will be separated from DAC and ADC without affecting test of other embedded cores. The test wrapper controller generates control signals both for switches and for multiplexers to determine the modes of the wrapper and each SHATI.Moreover, the pipelined parallel test manner is proposed to further reduce the test application time for multi-port or multicore test. We improve our wrapper design by adding SHATI to each test output port. When the current group of test stimuli is applied to test input ports, S2 of each output SHATI is turned off and all the test responses are held. Then S4 of each output SHATI is turned on to make the test responses sampled by ADC. It is categorized as pipelined parallel (PP) test manner. The example of the PP test manner is presented in parallel test mannerIn experiment results, w...
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