Most tasks in airborne scenarios are composed of neural networks (NN) and non-NN tasks. On the one hand, Deep neural networks (DNNs) have become the mainstream method of AI task processing. DNNs is accompanied by a large number of complex tensor calculations, as well as network delays and data privacy risks caused by using the cloud to process data. The combination of dedicated AI hardware accelerators and edge computing has become a new solution. On the other hand, dedicated AI hardware accelerators cannot efficiently handle non-NN class tasks (such as signal processing, control flow, etc.), so onboard systems need to design new hardware, complete compiler stacks, and runtime systems to handle non-NN class tasks. In order to effectively deal with multiple tasks in the airborne environment, the airborne computing system needs to establish a set of unified compilation and runtime system, which can optimize multiple tasks and be deployed on the heterogeneous computing platform to achieve "one compilation, multiple deployment". This paper analyzes the development of compiler and runtime systems at home and abroad, and compares the advantages and disadvantages of different technologies. Finally, this paper discusses the application scenarios of the compilation system and runtime in the airborne environment and the technical directions that need to be breakthroughs in the future, so as to provide guidance for the development of the airborne intelligent compilation and runtime system.
As an important technology and research direction to achieve AI, deep learning has been widely applied in the fields of computer vision, speech recognition, and natural language processing. How to effectively accelerate the computing power of deep learning has always been the focus of scientific research. Among various acceleration technologies, FPGA has the advantages of reconfiguration, high performance, small size, and low latency. As more and more FPGA-based neural network accelerators are developed, we notice there is a lack of a complete and detailed overview. In this paper, we give a comparative study of DNN accelerators on FPGA from the aspects of hardware structures, design ideas and optimization strategies. We further compare the performance of different acceleration technologies in different models and present the prospects of the FPGA accelerators for deep learning.
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