In this paper, mechanism of common-mode voltage of voltage source inverter is discussed in details, and it is pointed out that among the pulse width modulation (PWM) strategies for cascaded multi-level inverters (CMLI), those who based on inphase modulation of power-cell can cause common-mode voltage. Also, a novel SPWM for reducing common-mode voltage of cascaded multi-level inverter is presented, the pmposed SPWM strategy using nun-inphase modulation signals and third harmonic injection can totally eliminate common-mode voltage without extra hardware, and maintain high utilizing ratio of DC-Link voltage simultaneously. Theoretical analysis, simulation results are presented to verify the proposed strategy.Index Terms-Common-mode voltages, cascaded multi-level inverter, Nun-inphase modulation, PWM.
In this paper, we present a fast algorithm to derive the iii harmonic distortion in fully balanced Gm -C filters. It is based on Vi i state-space modeling and decomposition of the filter into a cascade g11 of an input stage, a core stage and an output stage. This approach _results in compact expressions for the distortion that involve explicitly the structural matrices of the filter and the values of the circuit elements. The algorithm was verified using a third-order low pass Butterworth filter designed in a 0.5,um CMOS process. The theoretical results are found to be in good agreement with CADENCE and MATLAB simulations. Fig. 1. The basic Gm-C block.
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