2003 IEEE PES Transmission and Distribution Conference and Exposition (IEEE Cat. No.03CH37495)
DOI: 10.1109/tdc.2003.1335374
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A novel PWM scheme to eliminate common-mode voltages in cascaded multi-level inverters

Abstract: In this paper, mechanism of common-mode voltage of voltage source inverter is discussed in details, and it is pointed out that among the pulse width modulation (PWM) strategies for cascaded multi-level inverters (CMLI), those who based on inphase modulation of power-cell can cause common-mode voltage. Also, a novel SPWM for reducing common-mode voltage of cascaded multi-level inverter is presented, the pmposed SPWM strategy using nun-inphase modulation signals and third harmonic injection can totally eliminate… Show more

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Cited by 2 publications
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“…as shown in Fig. 6(a), t x , t y , t 0 are separately the dwelling time of two neighboring vectors, zero-vectors V 0 or V 7 . T s is the switching period.…”
Section: Unipolarity and Bipolarity Of Pd-svmmentioning
confidence: 99%
See 1 more Smart Citation
“…as shown in Fig. 6(a), t x , t y , t 0 are separately the dwelling time of two neighboring vectors, zero-vectors V 0 or V 7 . T s is the switching period.…”
Section: Unipolarity and Bipolarity Of Pd-svmmentioning
confidence: 99%
“…Considering low voltage utilization of above improved SPWM, third-order harmonics are injected into modulation signals, and such modulation scheme has been applied in cascaded MV-VSD [7].…”
Section: Introductionmentioning
confidence: 99%