Micro-electro-mechanical-systems (MEMS) structures with different in-plane dimensions often need to be released simultaneously from the bulk of the wafer and a single dry etching or wet etching technique cannot fulfill all release requirements. In this paper we present a universally applicable solution to release MEMS structures with different surface areas in a controlled and uniform way, which combines isotropic etching of a sacrificial silicon support structure by xenon difluoride with a predefined etch surface made by deep reactive ion etching. Two applications of this Sacrificial Grid Release Technology are presented, in which MEMS devices are released in silicon-on-insulator wafers. The demonstrated applications involve the release of microstructures with in-plane dimensions ranging from tens of micrometers to a few millimeters. The sacrificial silicon structure provides mechanical support which allows freedom in process flow design for fragile MEMS structures. The release technique can also be used to separate the chips from the wafer.
In micro-machined micro-electromechanical systems (MEMS), refilled high-aspect-ratio trench structures are used for different applications. However, these trenches often show keyholes, which have an impact on the performance of the devices. In this paper, explanations are given on keyhole formation, and a method is presented for etching positively-tapered high-aspect ratio trenches with an optimised trench entrance to prevent keyhole formation. The trench etch is performed by a two-step Bosch-based process, in which the cycle time, platen power, and process pressure during the etch step of the Bosch cycle are studied to adjust the dimensions of the scallops and their location in the trench sidewall, which control the taper of the trench sidewall. It is demonstrated that the amount of chemical flux, being adjusted by the cycle time of the etch step in the Bosch cycle, relates the scallop height to the sidewall profile angle. The required positive tapering of 88° to 89° for a keyhole-free structure after a trench refill by low-pressure chemical vapour deposition is achieved by lowering the time of the etch step.
Known templating procedures mostly create out-ofplane nanowires where individual connections at both ends are complicated. Here we introduce a templating procedure for wafer scale fabrication of in-plane nanowires. The template fabrication process employs two simple interference lithography masking patterns and relies on self-aligned crystallographic processing. In-plane nanowires with diameters down to 10 nm can be fabricated wafer scale through this 3D templating procedure. As a first demonstration arrays of suspended silicon nitride wires have been created.
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