Plasmonic nanotweezers employing metallic nanoantennas provide a powerful tool for trapping nanoscale particles, but the strong heating effect resulting from light absorption limits widespread applications. Here, we propose an alldielectric nanotweezer harnessing quasi-bound states in the continuum (quasi-BICs) to enable the trapping of nanoscale objects with low laser power and a negligible heating effect. The quasi-BIC system provides very high electromagnetic field intensity enhancement that is an order of magnitude higher than plasmonic systems as well as high-quality-factor resonances comparable to photonic crystal cavities. Furthermore, the quasi-BIC metasurface tweezer array provides multiple optical hotspots with high field confinement and enhancement, thereby generating multiple trapping sites for the high-throughput trapping of nanometer-scale objects. By purposefully truncating the tips of the constituent elliptical nanoantennas in the quasi-BIC system to leverage the asymmetric field distribution, we demonstrate that the optical gradient forces can be further enhanced by a factor of 1.32 in comparison to the intact elliptical nanoantenna, which has attractive potential in subwavelength particle trapping applications. In addition, we show that trapped particles can improve the resonance mode of the cavity rather than suppress it in a symmetry-broken system, which in turn enhances the trapping process. Our study paves the way for applying quasi-BIC systems to low-power particle trapping and sensing applications and provides a new mechanism to harness the self-induced back-action.
The digital pixel driving scheme makes the organic light-emitting diode (OLED) microdisplays more immune to the pixel luminance variations and simplifies the circuit architecture and design flow compared to the analog pixel driving scheme. Additionally, it is easily applied in full digital systems. However, the data bottleneck becomes a notable problem as the number of pixels and gray levels grow dramatically. This paper will discuss the digital driving ability to achieve kilogray-levels for megapixel displays. The optimal scan strategy is proposed for creating ultra high gray levels and increasing light efficiency and contrast ratio. Two correction schemes are discussed to improve the gray level linearity. A 1280×1024×3 OLED-on-silicon microdisplay, with 4096 gray levels, is designed based on the optimal scan strategy. The circuit driver is integrated in the silicon backplane chip in the 0.35 μm 3.3 V-6 V dual voltage one polysilicon layer, four metal layers (1P4M) complementary metal-oxide semiconductor (CMOS) process with custom top metal. The design aspects of the optimal scan controller are also discussed. The test results show the gray level linearity of the correction schemes for the optimal scan strategy is acceptable by the human eye.
We report a dielectric nanoantenna system for the low-power optical trapping of nanoscale objects with ultra-low photothermal heating effect and enhanced trapping stability.
Gate-grounded NMOS (GGNMOS) devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGNMOS devices are measured using the transmission line pulsing (TLP) measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.
In this paper, a lot of CMOS devices with different device dimensions, spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection in 0.13um Silicide CMOS Technology. The dependences of layout parameters on ESD protection ability of GGNMOS are investigated by using the TLP (transmission line pulsing) measurement technique. A DC model for modeling ESD NMOS snapback characteristics is also presented in this paper.
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