This paper presents a 28-GHz CMOS four-element phased-array transceiver chip for the fifth-generation mobile network (5G) new radio (NR). The proposed transceiver is based on the local-oscillator (LO) phase-shifting architecture, and it achieves quasi-continuous phase tuning with less than 0.2-dB radio frequency (RF) gain variation and 0.3 • phase error. Accurate beam control with suppressed sidelobe level during beam steering could be supported by this work. At 28 GHz, a single-element transmitter-mode output P 1 dB of 15.7 dBm and a receiver-mode noise figure (NF) of 4.1 dB are achieved. The eight-element transceiver modules developed in this work are capable of scanning the beam from −50 • to +50 • with less than −9-dB sidelobe level. A saturated equivalent isotropic radiated power (EIRP) of 39.8 dBm is achieved at 0 • scan. In a 5-m overthe-air measurement, the proposed module demonstrates the first 512 quadrature amplitude modulation (QAM) constellation in the 28-GHz band. A data stream of 6.4 Gb/s in 256-QAM could be supported within a beam angle of ±50 • . The achieved maximum data rate is 15 Gb/s in 64-QAM. The proposed transceiver chip consumes 1.2 W/chip in transmitter mode and 0.59 W/chip in receiver mode.

This article presents the first 39-GHz phased-array transceiver (TRX) chipset for fifth-generation new radio (5G NR). The proposed transceiver chipset consists of 4 sub-array TRX elements with local-oscillator (LO) phase-shifting architecture and built-in calibration on phase and amplitude. The calibration scheme is proposed to alleviate phase and amplitude mismatch between each sub-array TRX element, especially for a large-array transceiver system in the base station (BS). Based on LO phase-shifting architecture, the transceiver has a 0.04-dB maximum gain variation over the 360 • full tuning range, allowing constant-gain characteristic during phase calibration. A phaseto-digital converter (PDC) and a high-resolution phase-detection mechanism are proposed for highly accurate phase calibration. The built-in calibration has a measured accuracy of 0.08°rms phase error and 0.01-dB rms amplitude error. Moreover, a pseudo-single-balanced mixer is proposed for LO-feedthrough (LOFT) cancellation and sub-array TRX LO-to-LO isolation. The transceiver is fabricated in standard 65-nm CMOS technology with flip-chip packaging. The 8TX-8RX phased-array transceiver module 1-m OTA measurement supports 5G NR 400-MHz 256-QAM OFDMA modulation with −30.0-dB EVM. The 64-element transceiver has a EIRP MAX of 53 dBm. The four-element chip consumes a power of 1.5 W in the TX mode and 0.5 W in the RX mode.

This article presents a low-cost and area-efficient 28-GHz CMOS phased-array beamformer chip for 5G millimeter-wave dual-polarized multiple-in-multiple-out (MIMO) (DP-MIMO) systems. A neutralized bi-directional technique is introduced in this work to reduce the chip area significantly. With the proposed technique, completely the same circuit chain is shared between the transmitter and receiver. To further minimize the area, an active bi-directional vector-summing phase shifter is also introduced. Area-efficient and high-resolution active phase shifting could be realized in both TX and RX modes. In measurement, the achieved saturated output power for the TX-mode beamformer is 15.1 dBm. The RX-mode noise figure is 4.2 dB at 28 GHz. To evaluate the over-the-air performance, 16 H+16 V sub-array modules are implemented in this work. Each of the sub-array modules consists of four 4 H+4 V chips. Two subarray modules in this work are capable of scanning the beam from −50 • to +50 •. A saturated EIRP of 45.6 dBm is realized by 32 TX-mode beamformers. Within 1-m distance, a maximum SC-mode data rate of 15 Gb/s and the 5G new radio downlink packets transmission in 256-QAM could be supported by the module. A 2 × 2 DP-MIMO communication is also demonstrated with two 5G new radio 64-QAM uplink streams. Thanks to

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This article introduces a power-efficient and lowcost CMOS 28-GHz phased-array beamformer supporting fifthgeneration (5G) dual-polarized multiple-in-multiple-out (MIMO) (DP-MIMO) operation. To improve the cross-polarization (crosspol.) isolation degraded by the antennas and propagation, a power-efficient analog-assisted cross-pol. leakage cancellation technique is implemented. After the high-accuracy cancellation, more than 41.3-dB cross-pol. isolation is maintained along with the transmitter array to the receiver array. The element-beamformer in this work adopts the compact neutralized bi-directional architecture featuring a minimized manufacturing cost. The proposed beamformer achieves 22% per path TX-mode efficiency and a 4.9-dB RX-mode noise figure. The required onchip area for the beamformer is only 0.48 mm 2 . In over-the-air measurement, a 64-element dual-polarized phased-array module achieves 52.2-dBm saturated effective isotropic radiated power (EIRP). The 5G standard-compliant OFDMA-mode modulated signals of up to 256-QAM could be supported by the 64-element modules. With the help of the cross-pol. leakage cancellation technique, the proposed array module realizes improved DP-MIMO EVMs even under severe polarization coupling and rotation conditions. The measured DP-MIMO EVMs are 3.4% in both 64-QAM and 256-QAM. The consumed power per

This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves a 265-µW ultra-lowpower operation. The proposed switching feedback can seamlessly change the DPLL from sampling operation to sub-sampling operation without disturbing the phase-locked state of the DPLL to reduce the number of building blocks that works at the oscillator frequency, leading to significant power reduction. With the reduced number of high-frequency circuits, scaling the reference frequency is fully used to reduce the power consumption of the DPLL. Together with an out-of-dead-zone detector and a duty-cycled frequency-locked loop running in the background, the switching feedback achieves robust frequency and phase acquisition at start-up and helps the sub-sampling PLL recover when large phase and frequency disturbances occur. A transformer-based stacked-g m oscillator is proposed to minimize the power consumption while providing the sufficient swing to drive the subsequent stages. A truncated constant-slope digital-to-time converter is proposed to improve the power efficiency while retaining good linearity. The proposed fractional-N DPLL consumes only 265 µW while achieving an integrated jitter of 2.8 ps and a worst case fractional spur of −52 dBc, which corresponds to a figure of merit (FOM) of −237 dB.

Background: To investigate the effect of caffeine citrate on the integrated brain electroencephalogram (EEG) of apnea and low birth weight infants. Methods: Overall, 212 infants with apnea and low birth weight admitted to Xuzhou Central Hospital from June 2016 to June 2018 were enrolled. The infants were divided into control group and observation group according to the random number table method, 106 cases in each group. Infants in control group were treated with aminophylline, and infants in the observation group were given caffeine citrate. All children were continuously tested by digital amplitude integrated brain function monitor. The amplitude-integrated electroencephalogram (aEEG) was used to detect sleep arousal cycle (Cy), graphic continuity (Co), lower edge amplitude value (LB) scores, aEEG continuous voltage and periodic occurrence rate, narrowband voltage and bandwidth. Results: After treatment, scores of Cy, Co and LB increased in both groups, and the scores were significantly higher in observation group than in control group (P=0.029, 0.017, 0.047). After treatment, continuous voltage positive rate, sleep-wake cycle occurrence rate, and narrow-band lower boundary voltage increased in both groups, and the values were significantly higher in observation group than in control group (P=0.011, 0.042). After treatment, aEEG detection bandwidth and the upper boundary voltage of the narrow band decreased in both groups, and the values were significantly lower in observation group than in control group (P=0.007, 0.020, 0.032). Conclusion: Citrate caffeine can alleviate the brain development of low-weight infants with apnea, improve brain electrical activity and promote brain function and maturity.

Photonic integrated circuits (PICs) suffer from birefringence due to high-index contrast. Polarisation handling devices improve the performance of the PICs by reducing the polarisation-dependent dispersion and loss. Furthermore, there is a growing interest in building polarisation division multiplexed transceivers using PICs, which require polarisation management. The authors provide an overview of the recent work on developing polarisation handling devices such as polarisation beam splitters and polarisers in indium phosphide and silicon-on-insulator platforms for optical communications and sensing applications. These devices expand the PICs library of polarisation handling devices and can be used to design more complex circuits with advanced or new functionalities. Polarisation beam splittersPBS is the basic building block in polarisation diversity circuits, which splits and combines light with different polarisations. The incoming signal polarisation is separated into two orthogonal polarisations (TE and TM) using a PBS, which enables