We investigated the influence of magnetic domain walls and magnetic fields on the thermal conductivity of suspended magnetic nanowires. The thermal conductivity of the nanowires was obtained using steady-state Joule heating to measure the change in resistance caused by spontaneous heating. The results showed that the thermal conductivity coefficients of straight and wavy magnetic nanowires decreased with an increase in the magnetic domain wall number, implying that the scattering between magnons and domain walls hindered the heat transport process. In addition, we proved that the magnetic field considerably reduced the thermal conductivity of a magnetic nanowire. The influence of magnetic domain walls and magnetic fields on the thermal conductivity of polycrystalline magnetic nanowires can be attributed to the scattering of long-wavelength spin waves mediated by intergrain exchange coupling.
Stackable 3DFETs such as FinFET using hybrid Si/ MoS 2 channels were developed using a fully CMOScompatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS 2 to Si fin and nanowire resulted in improved (+25%) I on,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device V th are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.I. Introduction 3DFETs can improve sub-20 nm CMOS node performance and substantially reduce supply voltage and short channel effects [1]. However, the traditional silicon channel must be replaced by high-mobility materials in future VLSI applications [2]-[3]. Heterogeneous twodimensional atomic crystals, namely, transition-metal dichalcogenide (TMD), have atomically smooth surface without dangling bounds and good mobility in CVD deposited films of atomic scale thickness are very attractive enablers of ultimately scaled transistors and 3D ICs [1,4]. However, a manufacturing flow must be realized using lowtemperature semiconductor process [5] and TMD by chemical vapor deposition (CVD) [6]. This paper presents the first CMOS process compatible TMD 3D transistor technology using novel hybrid Si/MoS 2 channel FinFET and NWFET with improved I on,n and matched V th of N and P devices. In comparison to previously published TMD transistors, this work reports the shortest gate length, thinnest gate dielectric, and first high performance at low voltage (Table 1 and Fig. 1).
II. Process Integration and Device FabricationThe reported work made use of a previously published low temperature Tri-gate FinFETs technology [7]. The fewlayer MoS 2 growth step was inserted after blocking oxide deposition and clean (see Figs. 2 and Fig. 4 for FinFET and Fig. 3 and Fig. 5 and for NWFET). The ~5nm SiO 2 on the surface of the Si fin is responsible for setting the desirable low and matched V th of N and P devices as shown later. A low-temperature activation process that involved microwave annealing [5] was used after hybrid MoS 2 deposition. In Figs. 6 and 7, the TEM images show the hybrid Si/MoS 2 channel trigate FinFET and NWFET respectively. Few-layer MoS 2 was successfully integrated into 3DFETs technology using low-temperature CVD with the number of MoS 2 layers determined by deposition duration (Figs. 8 and 9). The TiN gate over the hybrid Si/MoS 2 fins is 50 nm long (Fig. 10).
III. Results and Discussion A. MoS 2 Material AnalysisMoS 2 material analysis was performed over flat regions of the wafer and over the hybrid Si/MoS 2 fins. Figs. 11(a) and (b) show the S L-edge and Mo M-edge features of the MoS 2 clearly observed for both the films deposited on the flat Si substrate and over the hybrid Si/MoS 2 fins using X-ray absorption spectroscopy. Fig. 12 shows the X-ray absorption near the edge spectrum, which revealed that the Mo M-edge spectrum exhibited a peak in films deposited on flat Si substrate and on the hybrid Si/MoS 2 channel. Strong separated features ...
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