Two-dimensional (2D) transition metal dichalcogenides (TMDs)-based van der Waals (vdW) PN junctions have been used for heterojunction diodes, which basically utilize out-of-plane current across the junction interface. In fact, the same vdW PN junction structure can be utilized for another important device application, junction field effect transistors (JFETs), where in-plane current is possible along with 2D–2D heterojunction interface. Moreover, the 2D TMD-based JFET can use both p- and n-channel for low voltage operation, which might be its unique feature. Here we report vdW JFETs as an in-plane current device with heterojunction between semiconducting p- and n-TMDs. Since this vdW JFET would have low-density traps at the vdW interface unlike 2D TMD-based metal insulator semiconductor field effect transistors (MISFETs), little hysteresis of 0.0–0.1 V and best subthreshold swing of ~100 mV/dec were achieved. Easy saturation was observed either from n-channel or p-channel JFET as another advantage over 2D MISFETs, exhibiting early pinch-off at ~1 V. Operational gate voltage for threshold was near 0 V and our highest mobility reaches to ~>500 cm2/V·s for n-channel JFET with MoS2 channel. For 1 V JFET operation, our best ON/OFF current ratio was observed to be ~104.
Two-dimensional molybdenum disulfide (MoS 2) has substantial potential as a semiconducting material for devices. However, it is commonly prepared by mechanical exfoliation, which limits flake size to only a few micrometers, which is not sufficient for processes such as photolithography and circuit patterning. Chemical vapor deposition (CVD) has thus become a mainstream fabrication technique to achieve large-area MoS 2. However, reports of conventional photolithographic patterning of large-area 2D MoS 2-based devices with high mobilities and low switching voltages are rare. Here we fabricate CVD-grown large-area MoS 2 fieldeffect transistors (FETs) by photolithography and demonstrate their potential as switching and driving FETs for pixels in analog organic light-emitting diode (OLED) displays. We spin-coat an ultrathin hydrophobic polystyrene layer on an Al 2 O 3 dielectric, so that the uniformity of threshold voltage (V th) of the FETs might be improved. Our MoS 2 FETs show a high linear mobility of approximately 10 cm 2 V −1 s −1 , due to a large grain size around 60 μm, and a high ON/OFF current ratio of 10 8. Dynamic switching of blue and green OLED pixels is shown at~5 V, demonstrating their application potential.
depletion mode in general, that is to say, threshold voltage (V th ) is located quite away from 0 V whether the channel is nor p-type. [1,11,13,18,[22][23][24] This means that practical switching is not easy without applying high voltages; distinct OFF state is sometimes desperate in any smart functional/electrical applications involving either driving or sensing. [13,22,25,26] Second, gate bias induced hysteresis of 2D TMD transistor is, in fact, quite a critical issue for realizing prototype sensor applications because consistent dynamic property of real circuits should be secured both in ON and OFF states. [27][28][29][30] Several reports disclose that the electrical stability of the devices is significantly improved by the interface and surface states of the FET devices. [28,29,[31][32][33][34][35][36] For a good candidate to minimize the interfacial defect states in FET, the hexagonal boron nitride (h-BN), dangling-bond free dielectric layer, has been proposed. [37] Although this approach has been encouraging, h-BN is still expensive and less practical due to its special growth processes for good crystalline quality control. Hence, alternatives to replace h-BN have been suggested: self-assembled monolayer and hydrophobic organic insulating materials. [32,38] We have here chosen an ultrathin organic layer for two n-type TMD FETs: (8.46 nm) polystyrene (PS)-brush poly mer layer which is tethered by chlorosilane end group onto the oxide dielectric. The two TMD devices are n-MoS 2 and n-MoSe 2 FETs as a current driver, to be integrated into low-voltage organic P(VDF-TrFE) piezoelectric sensor circuit with organic light-emitting diode (OLED) indicator. The polymer PS-brush allows a hydrophobic, covalently bonded, ultrathin, and adherent layer directly on hydrophilic SiO 2 or Al 2 O 3 layer, providing hydroxyl group-minimized interface between TMD and dielectric layer. [39][40][41] To the best of our limited knowledge, PSbrush has never been reported for the TMD-based FETs while it is very robust as a conventional organic solvent. It is regarded that a standard lithography and lift-off process can be allowed. As a result, our TMD FETs with PS-brush show minimum hysteresis, but still display depletion mode behavior (V th was still larger than 0 V). Fortunately, the V th of n-MoSe 2 FET appears closer to 0 V than that of n-MoS 2 FETs, and its mobility could increase up to ≈11 cm 2 V −1 s −1 with electron doping by atomic layer deposited (ALD) Al 2 O 3 top layer. [42] When our TMD FETs were integrated into piezoelectric touch sensor circuit which allows instantaneous switching between ≈+5 and −5 V, the Toward any practical applications of 2D transition metal dichalcogenide (TMD) transistors, two issues are often met. First, threshold voltage (V th ) of usual TMD 2D field effect transistors (FETs) is located quite away from 0 V, making the device already on and less practical. Second, a large hysteresis exists during transistor operation. Here, hysteresis-minimized n-TMD FETs are fabricated using polymer-brush/channel...
Very recently, stacked two-dimensional materials have been studied, focusing on the van der Waals interaction at their stack junction interface. Here, we report field effect transistors (FETs) with stacked transition metal dichalcogenide (TMD) channels, where the heterojunction interface between two TMDs appears useful for nonvolatile or neuromorphic memory FETs. A few nanometer-thin WSe2 and MoTe2 flakes are vertically stacked on the gate dielectric, and bottom p-MoTe2 performs as a channel for hole transport. Interestingly, the WSe2/MoTe2 stack interface functions as a hole trapping site where traps behave in a nonvolatile manner, although trapping/detrapping can be controlled by gate voltage (V GS). Memory retention after high V GS pulse appears longer than 10000 s, and the Program/Erase ratio in a drain current is higher than 200. Moreover, the traps are delicately controllable even with small V GS, which indicates that a neuromorphic memory is also possible with our heterojunction stack FETs. Our stack channel FET demonstrates neuromorphic memory behavior of ∼94% recognition accuracy.
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