Nonvolatile and Neuromorphic Memory Devices Using Interfacial Traps in Two-Dimensional WSe₂/MoTe₂ Stack Channel

Abstract

Very recently, stacked two-dimensional materials have been studied, focusing on the van der Waals interaction at their stack junction interface. Here, we report field effect transistors (FETs) with stacked transition metal dichalcogenide (TMD) channels, where the heterojunction interface between two TMDs appears useful for nonvolatile or neuromorphic memory FETs. A few nanometer-thin WSe2 and MoTe2 flakes are vertically stacked on the gate dielectric, and bottom p-MoTe2 performs as a channel for hole transport. Interestingly, the WSe2/MoTe2 stack interface functions as a hole trapping site where traps behave in a nonvolatile manner, although trapping/detrapping can be controlled by gate voltage (V GS). Memory retention after high V GS pulse appears longer than 10000 s, and the Program/Erase ratio in a drain current is higher than 200. Moreover, the traps are delicately controllable even with small V GS, which indicates that a neuromorphic memory is also possible with our heterojunction stack FETs. Our stack channel FET demonstrates neuromorphic memory behavior of ∼94% recognition accuracy.

Structure modulation of two-dimensional transition metal chalcogenides: recent advances in methodology, mechanism and applications

“…Initial memory devices, for instance, memristors and memtransistors, depend on voltage-operated charge storage, referring to switchable low/high resistance states (LRS/HRS) and voltage hysteresis windows. 258,404,405 Charge trapping and storage processes in memristors and memtransistors are similar to neurotransmitter transportation during the signal transmission between neurons. Therefore, memristors and memtransistors are also called synaptic devices with excellent programming and erasing performances.…”

“…Therefore, semiconducting TMDs with atomic vacancies, doping atoms and heterointerfaces have become excellent candidates for memtransistor-type synaptic devices due to the localized states distributed in modulated point structures or interfaces. 405,406 As a demonstration, V-doped MoS 2 demonstrated considerable voltage hysteresis This journal is © The Royal Society of Chemistry 2023 during a voltage sweep from À100 V to 100 V, and then back to À100 V. 406 Under a V gs of 80 V, the electrons in the conduction bands of MoS 2 are injected into the trapping level corresponding to the V atoms to form programming states. Subsequently, they are detrapped and return to the conduction bands of MoS 2 to form erasing states under the V gs of À80 V, as shown in Fig.…”

Carbon Nanotube-Based Flexible Ferroelectric Synaptic Transistors for Neuromorphic Computing

“…Among these, synaptic transistors, which are three-terminal structured artificial synapses, have the advantages of good stability, controllable test parameters, and a clear operation mechanism. , Moreover, synaptic transistors can perform data reading and synaptic weight updating simultaneously, which better emulates the biological behavior and makes the synaptic transistor more suitable for artificial synapses than other types of devices. Synaptic transistors have been realized based on various mechanisms, including the electric double layer effect, − charge-trapping effect, ferroelectric effect, , mechanoplasticity, − etc. Ferroelectric field-effect transistors (FeFETs) have well-defined, controllable retarding hysteresis that is electric-field-driven, , which can well emulate the long-term and short-term biological synaptic plasticity via the existence of the coercive fields.…”

Energy-Efficient III–V Tunnel FET-Based Synaptic Device with Enhanced Charge Trapping Ability Utilizing Both Hot Hole and Hot Electron Injections for Analog Neuromorphic Computing

“…In addition, three-terminal synaptic devices based on the FET can be turned off during the off state and receive and read stimulus simultaneously, whereas two-terminal synaptic devices cannot. − Despite these advantages, there remain challenging issues that conventional metal-oxide-semiconductor FET (MOSFET)-based charge trap synapses require a strong stimulus with a high pulse amplitude and a long pulse width for synaptic weight update because of their inefficient carrier injection into the charge trap layer. It consequently causes a slow speed operation and a large power consumption. − Therefore, a highly efficient charge trap scheme and device structure are essential for energy-efficient ANN systems.…”