This paper discusses silicon complementary metal–oxide–semiconductor (CMOS) field-effect transistors with dual work function gates (DWFG) to improve transconductance (g
m) and drain conductance (g
ds) characteristics. For a n-channel metal–oxide–semiconductor field-effect transistor (MOSFET) device, the polycrystalline silicon (poly-Si) gate on the source and drain side are doped p+ and n+, respectively and vice versa for a p-channel MOSFET. The work function difference in a poly-Si gate affects channel potential distribution and increases the lateral electric field inside the channel. The increased electric field inside the channel improves carrier drift velocity. Experimental results from the fabricated DWFG devices show improved g
m and g
ds over conventional single work function gate devices.
Abstract-New developments in nanoelectronics are promising a new generation of computing, which has greater focus on device capabilities. Further to many applications of memristors in artificial intelligence or artificial biological systems, they enable reconfigurable nanoelectronics and also provide new paradigms in application specific integrated circuits (ASIC) and field programmable gate arrays (FPGA). Providing a significant reduction in area and an unprecedented memory capacity and device density are the potential features memristors for Integrated Circuits (IC).This work reviews the memristor and its characteristics and provides a SPICE macro-model of the memristors which helps us to develop models for the SPICE based circuit analysis tools like HSpice and Spectre. An insight into the memristor device recalling the quasi-static expansion of Maxwell's equations and a review on Chua's argumentation about the memristor through the electromagnetic theory are also given.
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