Cameras for automobile, scientific and industrial applications often require very wide linear dynamic range with consistently high SNR over the entire illumination range. It is expected that CMOS image sensors are used for such applications. A sophisticated wide dynamic range CMOS image sensor using a multiple sampling technique and in-pixel ADC is developed [1][2] and a digital dynamic range of 16b (65536:1) is achieved. However, the in-pixel ADC requires six transistors in each pixel. A wide dynamic range image sensor with a high-speed high-resolution column parallel ADC and synthesis of multiple exposure-time signals captured with a high-speed image signal readout is described in this paper. The developed CMOS image sensor with standard 3-transistor active pixels and integrating 12b column parallel cyclic ADCs has a 19.5b (117dB) digital dynamic range and is very flexible for setting the image capturing conditions. Figure 19.3.1 displays the readout timing of multiple exposuretime signals in the CMOS image sensor. This diagram shows an example of the case where the sensor has five vertical pixels and four different exposure-time signals are read. Here, each exposure-time signal is read in a time slot equal to 1/6 of the frame period. The long accumulation-time (LA) signals occupy three slots for signal accumulation. Using times slot for reading the LA signals, the signals are accumulated during the first short accumulation-time (SA). Very short accumulation-time (VSA) and extremely short accumulation time (ESA) signals are accumulated using the time slots for reading the SA and VSA signals, respectively. Using dual vertical shift registers, a delayed reset pulse is generated to control the accumulation time of the SA, VSA and ESA signals. For example, with 1/10, 1/120 and 1/1440 of the accumulation time of LA signals for SA, VSA and ESA, respectively, the dynamic range can be expanded by a factor of 1440, and the accumulation-time ratios of LA to SA, SA to VSA and VSA to ESA are 10, 12 and 12, respectively. This relativelysmall exposure-time ratio results in keeping a high SNR in the entire illumination range. At the expense of external processing, the dynamic range compression characteristics are flexibly and adaptively changed to the scene. When compared with the method presented in [3], the high-speed readout method has three times higher dynamic range because the horizontal readout cycle is reduced by a factor of three. Figure 19.3.2 shows the circuit schematic of the cyclic ADC with a noise canceling function. A column parallel 2-stage cyclic ADC with 9b and a noise canceller with a CMOS image sensor requires three operational amplifiers and ten sampling capacitors [4]. The cyclic ADC proposed requires only one operational amplifier and six sampling capacitors as shown in Fig. 19.3.2. Figure 19.3.3 depicts the noise cancellation and the cyclic A/D conversion. Single-ended circuits are used in Fig. 19.3.3 for simplicity although the actual circuits are of fully differential. In the signal sampling phase of...
A ultra wide dynamic range image sensor with a linear response is presented. The proposed extremely short accumulation (ESA) signal readout technique enables the dynamic range of image sensor to be expanded up to 142dB. Including the ESA signals, total of 4 different accumulation time signals are read out in one frame based on burst readout mode. To achieve the high-speed readout required for the multiple exposure signals, column parallel A/D converters are integrated at the upper and lower sides of pixel array. The improved column parallel cyclic 12-b ADC with a built-in CDS circuit has the differential nonlinearity of ±0.3LSB. I. INTRODUCTIONA wide dynamic range (DR) image sensor which has a linear response is required for many imaging applications such as automobiles, security systems and industrial applications. A wide linear response for whole illumination range with high resolution enables reliable image recognition and signal processing. CMOS image sensors are suitable for such applications.Many methods to expand the dynamic range of image sensors using CMOS technology have been reported. Logarithmic compression is a well-known method to expand a dynamic range of image sensors [1]. However, the logarithmic image sensor has an image lag due to slow response time for a lower light illumination. In order to overcome the image lag and increase a sensitivity of image sensors at a lower illumination range, a linear-logarithmic image sensor was also reported [2]. It has a linear and a logarithmic response at dark and bright illumination, respectively. However, such non-linear image sensors are difficult to reduce a random noise, like a dark current and a reset noise due to a limitation of pixel structure.Representative methods which have a linear output response are dual-sampling [3], multi sampling method using in-pixel ADC [4], and an in-pixel overflow integration capacitor [5]. In these wide DR image sensors, the dynamic range is limited
Abstract:A wide dynamic range CMOS image sensor based on a new active pixel structure with a pinned photodiode is proposed and evaluated with device simulations. The proposed pixel device has a linear and a logarithmic characteristics in low and high illumination region, respectively. The technique of direct detection of photodiode potential leads to a wide logarithmic response compared with the conventional linear-log wide DR image sensor with pinned photo diode. Keywords: CMOS image sensor, wide dynamic range, floating gate Classification: Photonics devices, circuits, and systems References[1] M. Sasaki, S. Kawahito, M. Mase, and Y. Tadokoro, "Method to extend dynamic range of CMOS image sensor using different frame-rate readout,"
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