This paper proposes a D-band push-push voltage controlled oscillator implemented using 22nm FDSOI CMOS technology. The back-gate controls are employed to achieve a wide frequency tuning range (FTR) and low power consumption. Inductive coupling with the dummy fill blocks are optimized to improve the resonator quality factor. The measured results demonstrate a wide tuning range of 11.6% from 138-155.1 GHz with a supply voltage of 0.9 V. The output power of the VCO is -16 dBm at a center frequency of 146.6 GHz with a phase noise of -90.1 dBc/Hz at 10 MHz offset. The VCO consumes a low power of 12.2 mW with a compact area of 259x249 µm 2 . The corresponding F OMT is -163.9 dBc/Hz.

This paper presents the design of two high efficiency fundamental voltage controlled oscillators (VCO) for sub-THz applications. The design optimizes the transistor for voltage gain, swing and PAE at the operating frequency to achieve 21% and 7% DC-to-RF efficiencies. The varactor and back-gate voltages are utilized for tuning control. The back-gate controls improves the relative tuning range of the VCOs by ∼50%. Layout techniques are employed in the transistor and inductor to improve the VCO frequency. The two VCOs are implemented in 22nm CMOS FDSOI, oscillate at 108.7 GHz and 124 GHz having an output power of 3.41 and -1.45 dBm with a tuning range of 3.4% and 3.7%, respectively. The chip operates at a supply voltage of 0.7V and an IBIAS of 1.4mA with a core power consumption of 10.2mW and 9.9mW, respectively. The active area is 0.095x0.087 mm 2 .

Millimeter wave oscillators are of particular interest towards future communications and sensing as frequency multiplication of local oscillator signal is resulting in degraded performance. At high frequencies, the quality (Q) factor of the LC tank is degraded. Thus, a higher transconductance (GM) size is required to compensate the losses, thereby consuming high power. Numerous techniques have been adopted to reduce the power consumption of a cross-coupled LC voltage controlled oscillator (VCO) and to improve the negative resistance (Rneg) associated to it. One of them utilizes inductors in the cross-coupled pair. In this paper, we examine the tradeoffs of this inductor to improve negative resistance above 100 GHz. For the analysis, the transistor model is being verified with the simplified small-signal equivalent model. Moreover, we have studied the inductor influence on the transition frequencies of the cross-coupled pair. The restrictions of this technique at high frequencies is investigated. To study the benefits of this technique, an oscillator core is designed and simulated using the 22nm FDSOI CMOS process. It exhibits a tuning range of 5.4% from 125.5 GHz to 132.5 GHz, and phase noise from -101.23 dBc/Hz to -102.0381 dBc/Hz at 10 MHz offset over the entire tuning range. The VCO consumes power of 17 mW. In simulations, an improvement in power consumption by 4.3 mW and phase noise by 1.5 dBc/Hz were achieved when compared to conventional LC Tank VCO.