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Device FabricationExtreme high-performance n-and pFETs are achieved as Fig. 1 schematically shows the cross sectional structures 1300 and 1000 uA/um at Ioff= 100 nA/um and Vdd = 1.0 V, of n-and pFETs with damascene metal/high-k gate stacks. respectively, by applying newly proposed booster The process flow is shown in Fig. 2. For the pFETs, SiGe technologies. The combination of top-cut dual-stress liners epitaxial growth after Si recess was carried out. 1.6-GPa and damascene gate remarkably enhances channel stress tensile stress SiN liner (t-SL) and 2.0-GPa compressive especially for shorter gate lengths. High-Ion pFETs with stress layers (c-SL) were deposited after Ni silicidation for compressive stress liners and embedded SiGe source/drain n-and pFETs, respectively. After PMD deposition, the stress are performed by using ALD-TiN/HfO2 damascene gate liners were cut only on the top of the dummy gates by using stacks with Tinv = 1.4 nm on (100) substrates. On the other CMP to expose dummy gate tops. After dummy gate hand, nFETs with tensile stress liners are obtained by using removal, ozone water treatment was used prior to HfSix/HfO2 damascene gate stacks with Tinv = 1.4 nm.ALD-HfO2 deposition to improve mobility in the thinner Tinv region [8]. Metal/high-k gate stacks were formed with Introduction HfSix/HfO2 and TiN/HfO2 for n-and pFETs, respectively. Fig. 3 shows a cross-sectional TEM image of a pFET. For Metal/high-k gate stacks have been recently investigated reference, metal/high-k and poly-Si/SiO2 gate MOSFETs for Tinv scaling and gate-leakage-current reduction. The without stress liners were also fabricated. gate-last damascene process having band-edge work-function dual-metal is one of the great candidates to Stress Simulations for n-and pFETs achieve high-performance MOSFETs [1-3]. SiN stress liner is another important technology to enhance drivability of Lateral (Sxx) and vertical (Szz) stress distributions around devices [4,5]. Furthermore, it has been reported that the the channel of pFETs are shown in Fig. 4, where Lgate = 40 discontinuous stress liners in fully-silicided (FUSI) gate nm, and eSiGe and c-SL thicknesses are 80 and 60 nm, MOSFETs maintain high mobility [6]. On the other hand, respectively. Fig. 5 shows average stress distributions we have reported that the damascene gate process between gate center and edge at a depth of Inm below the considerably enhances channel stress from embedded SiGe channel surface, and relative hole mobilities, correlated to (eSiGe) source/drain, due to dummy gate removal [7]. the four process steps of Fig. 4. The relative mobility was Therefore, it might be considered that the damascene gate calculated using piezoresistance coefficients [9], process aggressively enhances the drivability caused by the SiN stress liners. Ahx = -0.718 Sxx + 0.663 Syy + 0.011 S.z (l) In this paper, the channel stresses from both the top-cut Pho dual stress liners and eSiGe S/D in the damascene process Pexx 1 + 0.316S + 0.176S -0.534S (2) are firstly discussed using stress and mob...

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