Low power, high resolution and high-speed ADCs are becoming increasingly important with advancements in portable electronics, from mobile phones and pagers to CD players and MP3 players. This is certainly not feasible on a handheld device which is why new ADC techniques must be developed. They are becoming increasingly attractive to major data converter manufacturers and their designers because pipeline ADCs provide an optimal balance of scale, speed, resolution, power dissipation and analogue design effort. Because of latency and errors in comparators & gain stages in pipelined ADCs, the need arises for digital error correction mechanism. The digital error correction logic will be implemented for 8-bit ADC using 1.5 bits per stage. While designing we are considering important parameters of CMOS like propagation delay performance and power dissipation. The VLSI realization of digital arithmetic is implemented using TANNER EDA software tool using 0.18µm CMOS process.
The main building block of microprocessors, microcontrollers, and digital signal processors is an arithmetic logic unit (ALU). The performance of ALU depends on its adder design. The Carry Propagation Delay (CPD), area and power are the important metrics in the structure of the adder. In this work, area and power analysis of carry select adder are presented. In this adder, the CPD is minimized with the common Boolean logic. The power and area of the adder are optimized by replacing CMOS gates with transmission gates. In this technique, the transistor count is greatly reduced from 987 to 512 for a 16-bit carry select adder. In addition, the power consumption is minimized from 0.63mW to 0.018mW and the power delay product is minimized from 0.53mW-ns to 0.021mW-ns.
The addition is common in hardware for the microprocessor and digital signal processor (DSP), and an adder is used to execute the addition. The Adder should feature high speed and low power for real-time applications. An effective adder architecture principally advances the performance of microprocessors and DSP systems. The carry propagation delay (CPD) is the main apprehension in the design of adder architecture. To address CPD, a new Carry Look-Ahead architecture is proposed, in which the carry propagation is scheduled before the calculation of the final sum using carry look–ahead (CLA) method. A quantitative estimate shows that the Area Delay Product (ADP) of proposed adder architecture is minimized by 10% as compared with the existing adders’ architectures.
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