Area-Power Analysis of Carry Select Adder using Transmission gates

Abstract

The main building block of microprocessors, microcontrollers, and digital signal processors is an arithmetic logic unit (ALU). The performance of ALU depends on its adder design. The Carry Propagation Delay (CPD), area and power are the important metrics in the structure of the adder. In this work, area and power analysis of carry select adder are presented. In this adder, the CPD is minimized with the common Boolean logic. The power and area of the adder are optimized by replacing CMOS gates with transmission gates. In this technique, the transistor count is greatly reduced from 987 to 512 for a 16-bit carry select adder. In addition, the power consumption is minimized from 0.63mW to 0.018mW and the power delay product is minimized from 0.53mW-ns to 0.021mW-ns.