The Timepix3, hybrid pixel detector (HPD) readout chip, a successor to the Timepix [1] chip, can record time-of-arrival (ToA) and time-over-threshold (ToT) simultaneously in each pixel. ToA information is recorded in a 14-bit register at 40 MHz and can be refined by a further 4 bits with a nominal resolution of 1.5625 ns (640 MHz). ToT is recorded in a 10-bit overflow controlled counter at 40 MHz. Pixels can be programmed to record 14 bits of integral ToT and 10 bits of event counting, both at 40 MHz. The chip is designed in 130 nm CMOS and contains 256 × 256 pixel channels (55 × 55 µm 2 ). The chip, which has more than 170 M transistors, has been conceived as a general-purpose readout chip for HPDs used in a wide range of applications. Common requirements of these applications are operation without a trigger signal, and sparse readout where only pixels containing event information are read out.A new architecture has been designed for sparse readout and can achieve a throughput of up to 40 Mhits/s/cm 2 . The flexible architecture offers readout schemes ranging from serial (one link) readout (40 Mbps) to faster parallel (up to 8 links) readout of 5.12 Gbps. In the ToA/ToT operation

Monolithic Active Pixel Sensors (MAPS) have been developed since the late 1990s based on silicon substrates with a thin epitaxial layer (thickness of 10-15 µm) in which charge is collected on an electrode, albeit by disordered and slow diffusion rather than by drift in a directed electric field. As a consequence, the signal is small (≈ 1000 e -) and the radiation tolerance is much below the LHC requirements by factors of 100 to 1000. In this paper we present the development of a fully Depleted Monolithic Active Pixel Sensors (DMAPS) based on a high resistivity substrate allowing the creation of a fully depleted detection volume. This concept overcomes the inherent limitations of charge collection by diffusion in the standard MAPS designs. We present results from a test chip EPCB01 designed in a commercial 150 nm CMOS technology. The technology provides a thin (∼ 50 µm) high resistivity n-type silicon substrate as well as an additional deep p-well which allows to integrate full CMOS circuitry inside the pixel. Different matrix types with several variants of collection electrodes have been implemented. Measurements of the analog performance of this first implementation of DMAPS pixels will be presented.

In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256 x 256 pixels with a pixel pitch of 55 μm. The first architecture has been implemented in the Timepix3 chip, and this is presented together with initial measurements. Simulation results and measured data are compared. The second architecture has been designed for Velopix, a readout chip planned for the LHCb VELO upgrade. Unlike Timepix3, this has to be tolerant to radiation-induced single-event effects. Results from post-layout simulations are shown with the circuit architectures.

Traditional analog ASICs use filtered signals passing a constant threshold to obtain the trigger time of induced signals from a pixelated CdZnTe detector. However, poor signal-tonoise ratio (SNR) and variable leading edge of the cathode signal cause higher trigger threshold and lower timing resolution. In this study, only the anode channels of analog ASICs are used to trigger the system, and the corresponding cathode waveforms are sampled by an external high-speed analog-to-digital converter (ADC). Rise time and amplitude of the cathode signal can be obtained by digital signal processing (DSP), which achieves a good timing resolution and eliminates the ballistic deficit. The test was carried out on a system with 2 × 2 detector array. The reconstructed depths are improved by using cathode waveforms, and the optimal energy resolution of 0.54% full width at half-maximum (FWHM) at 662 keV for all single-pixel events has been observed in one detector.

The paper presents a design of CMOS Pixel Sensor (CPS) using the vertical integration technology (3DIT), expected to alleviate the most essential limitations of 2D-CPS. Our objective is to develop an intelligent architecture in order to meet the requirements of the innermost layer of the International Linear Collider (ILC) vertex detectors, which are particularly demanding in spatial resolution of less than 3 µm and associated frame readout time of 10 µs. The sensor, with a pixel pitch of 23 µm, will be composed of 3-tiers Integrated Circuits (IC) with different functionalities: detection with in pixel analogue processing, pixel-level 3-bit Analogue to Digital Conversion (ADC) and fast parallel sparse readout.