As the scaling proceeds, the transverse electric field increase, and a mobility attenuation phenomenon becomes of primordial interest. Indeed, the high transverse electric field is generally ascribed [1] to surface roughness scattering in the channel and consequently reduce effective mobility of carriers. In short channel MOSFET, the Source-Drain resistance Rsa influence strongly the effective mobility. The aim of this work is therefore to propose an original method especially conceived for the extraction of the series resistance Rsd. Using the approach of the Surface Roughness Scattering which enables a consistent modelling of the mobility to be obtained from low to high electric field [2], this allow to determine all model parameters in particular a Series Resistance from the plot of the transfer characteristic drain current Id versus gate voltage Vg Curves.

Abstruct-A new method for drain saturation voltage extraction in submicron MOSFETs is presented. It is based bn measurements of the partial derivative of the impact ionization rate. The method has been tested using different channel length MOSFET devices and compared with others methods. I.INIRODUCTIONrain saturation voltage Vdm is an important D parameter in MOSFET modelling and process control. The existing method for V&, versus the gate voltage Yg extraction can be divided into two categories. The first [1,2], is based' on Id-Vd plotted curves where Id is the drain cumnt and Vd is the drain voltage and the second [3,4], is based on the unique dependence (Vd-Vdd of the ratio (Isub/Iq where Isub represent the substrate current. In this letter a new technique for an accurate determination of drain saturation voltage can be classed with the second methods, and give directly the continuou Vd,,(V@ characteristics. U.THEORYGenerally, according to the lucky electron model [5], since the impact ionization rate is proportional to exp[-B/(Vd-Vd,,J], where B is a constant and (Vd-Vd& is proportional to the drain field. In the literature [6], we found one of the follows expressions of the ratio Isub/Id Isub/Id = A exp[-B/(Vd-Vd&(1) Or Isub/Id = A '(Vd-Vdd exp[-BY(Vd-VdJ(2) Where A', A, B' and B are constants. B' and B have a voltage dimension and are function of the carrier mean free path, and of the length pinchsff region. We note that (I) and (2) are all dependants on the difference (Vd-Vdd. We pose X(Vg,Vd) = Vd-Vdmt and Y(Vg Vd) = hb/Id, the ratio of partial derivative Y on Wand Vg can be calculated as : The characteristic Vd, (v@ is also obtained by the following integral : dY avd m. RESULTS AND DISCUSSION The previous analysis is applied at room temperature on the N Channel CNET MOSFET devices, with channel width Wis 50 pm and channel lengths are (L = 0.9,1.5 and 10 pm) the Light Doped Drain Region (LDD) doping is 5.10J3/ cm3, the channel doping Nu ranging between 1OJSandldb/cm3, the oxide thickness tm is 25 nm The method is also compared to the Chan et a1 method [3]. 0.0 0.S 1,0 1.5 2.0 2.5 3.0 3,s vs (V) Fig.1 Vd, versus Vg characteristics for three different Channel lengths. (L = 0.9, 1.5 and lOpm).The figure 1 shows Vdw (V& characteristics for three different channel lengths (0.9, 1.5 and 10 pm) . The 63

In this letter, an accurate method for extracting the critical fieldEcin short channel MOSFET's is presented. The principle of this method is based on the comparison between two models which give drain saturation voltage evolution against gate voltageVdsat(Vg)continuously. The results obtained by this technique have shown better agreement with measurements data and have allow in the same time to determine the validity domain of Sodini's law [1].

The aim of this work is to study the physical obstacles introduced by the use of high-k MOSFETs structures and discuss basic problems associated with high-k candidates currently investigated such as low carrier mobility and parasitic interfacial layers and to present other ways to reduce the undesirable secondary effects when one replaces silicon with a high dielectric oxyde (high-k). We will show that use of the nitride allows reducing the effects of the interfacial layers with an acceptable reduction rate of mobility.

In order to characterise the velocity saturation phenomena in short channel MOSFET's, a simple method is proposed in this work. It is based on the comparison between transistor behaviour in ohmic and saturation regime respectively. Therefore, the MOSFET characteristicId0(Vd). avoiding velocity saturation phenomena, can be obtained from ohmic characteristicId(Vg)and compared with the experimental characteristicId(Vd).