Cu nanoparticle paste has become one of the alternative materials for conventional high-temperature packaging, but this sintering process is significantly inhibited by copper oxides. In this paper, the activated formic acid atmosphere was used to achieve high-strength Cu–Cu bonding at low temperature. When sintered at a temperature of 275 °C for 30 min with a pressure of 5 MPa, a shear strength of more than 70 MPa was achieved. In contrast to formic acid atmosphere, the hydrogen radicals generated by activated formic acid atmosphere facilitated the rapid evaporation of the solvent during preheating process. Moreover, the hydrogen radicals effectively reduced of the oxides on the surface of the Cu nanoparticle resulting in a higher shear strength. This Cu nanoparticle sintering method has great potential in the field of power device integration in future.
A novel bonding process using Ag agglomerates paste prepared by Ag2O reduction has been proposed, which solved the problem of Cu substrate oxidation in the conventional Ag2O sintering process for Cu–Cu bonding. By applying the Ag agglomerate paste to Ag–Ag bonding, a shear strength of 28.3 MPa at 150 °C was obtained. Further studies showed that the optimum sintering temperature was at 225 °C, and a shear strength of 46.4 MPa was obtained. In addition, a shear strength of 20 MPa was obtained at 225 °C for Cu–Cu bonding. Compared to common Ag pastes, the results in this paper revealed that the sintering behavior of Ag agglomerates was unique, and the sintering mechanisms for Ag–Ag and Cu–Cu bonding were also discussed.
Critical path replica (CPR) is a widely used technique in synchronous digital circuit design. However, the existing CPR technique cannot accurately reflect the timing of the circuit due to local process variations (LPV). An improved CPR technique based on load capacitance matching (LCM) is proposed in this paper, which can track critical path delay across wide voltage range. The impact of LPV is simulated under wide voltage range, and a configurable delay line is designed to eliminate the effect of LPV. Furthermore, a low overhead mixed-threshold transition detector (TD) circuit is also proposed to monitor timing violations of the replica path, which generate an 'error' signal used to dynamically regulate the chip's operating voltage. The proposed techniques are implemented on a CORDIC chip using the 55-nm CMOS process. Simulation results show that in the near-threshold voltage (NTV) region, the supply voltage can be reduced from 0.8 to 0.6 V, enabling a maximum of 42.6% power saving at the TT corner, 25°C with lesser than 1% area overhead as compared to the baseline design.
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