This paper presents the first silicon-proven stochastic LDPC decoder to support multiple code rates for IEEE 802.15.3c applications. The critical path is improved by a reconfigurable stochastic check node unit (CNU) and variable node unit (VNU); therefore, a high throughput scheme can be realized with 768 MHz clock frequency. To achieve higher hardware and energy efficiency, the reduced complexity architecture of tracking forecast memory is experimentally investigated to implement the variable node units for IEEE 802.15.3c applications. Based on the properties of parity check matrices and stochastic arithmetic, the optimized routing networks with re-permutation techniques are adopted to enhance chip utilization. Considering the measurement uncertainties, a delay-lock loop with isolated power domain and a test environment consisting of an encoder, an AWGN generator and bypass circuits are also designed for inner clock and information generation. With these features, our proposed fully parallel LDPC decoder chip fabricated in 90-nm CMOS process with 760.3 K gate count can achieve 7.92 Gb/s data rate and power consumption of 437.2 mW under 1.2 V supply voltage. Compared to the state-of-the-art IEEE 802.15.3c LDPC decoder chips, our proposed chip achieves over 90% reduction of routing wires, 73.8% and 11.5% enhancement of hardware and energy efficiency, respectively.Index Terms-Error correction, IEEE 802.15.3c, iterative decoding, low-density parity-check (LDPC) code, stochastic decoding.
This paper presents an area-efficient relaxed halfstochastic nonbinary LDPC (NB-LDPC) decoder. A novel decoding algorithm, namely cumulative tracking forecast memory with concealing channel values (CTFM-CC) is proposed to reduce algorithm complexity and maintain bit-error-rate performance as well. Furthermore, the hardware complexity of variable node units is reduced through a truncated architecture, which only keeps the most reliable n probability density functions. To deal with the sum-product algorithm (SPA)-to-Stochastic conversion of VNU, a dynamic random number generation method which is used for sampling a stochastic symbol is also proposed. With these features, a (168, 84) regular-(2,4) NB-LDPC code over GF(16) decoder is implemented in 90-nm process. According to the results of post-layout simulation, this decoder can deliver a throughput of 1.13 Gb/s with a hardware efficiency of 0.90 Mb/s/K-gate at 286 MHz. Compared to related rate-1/2 NB-LDPC decoders, the proposed decoder achieves the highest hardware efficiency with similar error-correcting capability.
With a Viterbi decoder, the bit error probability of a communication system can be reduced. However, the power consumption of exploiting Viterbi decoder is an overhead to systems. In the Viterbi decoder, the survivor memory unit (SMU) is the most power critical due to data exchanging. A low-power radix-4 Viterbi decoder based on a differential cascode voltage switch with pass gate (DCVSPG) pulsed latch with sharing technique is proposed to process two bits concurrently. The dynamic power of SMU is reduced by the sharing technique. Moreover, the smaller clock loading also leads to power-efficient characteristic. Based on UMC 90nm process, the simulation results show the proposed Viterbi decoder with sharing technique could achieve better power scheme with energy efficiency 0.128 nJ/bit at 0.9V.
While global environment is proceeding globalization and internationalization, traditional logistics management can not be coped with the change. Therefore, to be the winner, supply chain integrating is necessary. Domestic car manufacturers take supply chain integrating to cope with the pressure of the market in now and future, and they hope to keep the competitive advantage. In view of this, from viewpoint of 3C model, we use case study to discuss and analysis supply chain integrating on company C which is the benchmark of the car industry, and then we offer a good suggestion to car manufacturers and future study direction.
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