A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications

Abstract

This paper presents the first silicon-proven stochastic LDPC decoder to support multiple code rates for IEEE 802.15.3c applications. The critical path is improved by a reconfigurable stochastic check node unit (CNU) and variable node unit (VNU); therefore, a high throughput scheme can be realized with 768 MHz clock frequency. To achieve higher hardware and energy efficiency, the reduced complexity architecture of tracking forecast memory is experimentally investigated to implement the variable node units for IEEE 802.15.3c applications. Based on the properties of parity check matrices and stochastic arithmetic, the optimized routing networks with re-permutation techniques are adopted to enhance chip utilization. Considering the measurement uncertainties, a delay-lock loop with isolated power domain and a test environment consisting of an encoder, an AWGN generator and bypass circuits are also designed for inner clock and information generation. With these features, our proposed fully parallel LDPC decoder chip fabricated in 90-nm CMOS process with 760.3 K gate count can achieve 7.92 Gb/s data rate and power consumption of 437.2 mW under 1.2 V supply voltage. Compared to the state-of-the-art IEEE 802.15.3c LDPC decoder chips, our proposed chip achieves over 90% reduction of routing wires, 73.8% and 11.5% enhancement of hardware and energy efficiency, respectively.Index Terms-Error correction, IEEE 802.15.3c, iterative decoding, low-density parity-check (LDPC) code, stochastic decoding.

Introduction to stochastic computing and its challenges

“…Because they handle very long code words (thousands of bits), LDPC decoders require extremely complex logic if implemented by conventional binary means; they also employ probabilistic decoding algorithms. These features suggest that LDPC decoders can exploit the small size, error tolerance, and probabilistic aspects of SC to achieve high area efficiency and throughput, as has been demonstrated very recently [12].…”

An Area-efficient Half-row Pipelined Layered LDPC Decoder Architecture

“…First of all, analysis results show that the proposed halfrow pipelined layered LDPC decoder reduces the complexity of nearly all components by half, compared to the fully parallel pipelined layer LDPC decoder design of Kumawat et al [19]. Moreover, the proposed decoder reduces the major area-consuming components, like adders, sign magnitude conversion (SMC), and min comparators, compared to flooding decoders [18,20]. This will lead to a reduction in hardware complexity for the proposed half-row LDPC decoder as these components are the main contributor of logic resources in the decoder architecture.…”

Energy Detector based Time of Arrival Estimation using a Neural Network with Millimeter Wave Signals

“…Several statistical channel models have been developed for 60 GHz signals such as those in the IEEE 802.15.3c and ECMA 387 standards. The IEEE 802.15.3c standard [21] was developed to support the transmission of data within a few meters at a minimum data rate of 2 Gbps. Both line of sight (LOS) and non-line of sight (NLOS) channel models are provided for indoor residential, indoor office, industrial, outdoor, and open outdoor environments [22] [23].…”