Three-dimensional (3D) printing with conductive polymer nanocomposites provides an attractive strategy for the “on-demand” fabrication of electrical devices. This paper demonstrates a family of highly conductive multimaterial composites that can be directly printed into ready-to-use multifunctional electrical devices using a flexible solvent-cast 3D printing technique. The new material design leverages the high aspect ratio and low contact resistance of the hybrid silver-coated carbon nanofibers (Ag@CNFs) with the excellent 3D printability of the thermoplastic polymer. The achieved nanocomposites are capable of printing in open air under ambient conditions, meanwhile presenting a low percolation threshold (i.e., <6 vol %) and high electrical conductivity (i.e., >2.1 × 105 S/m) without any post-treatments. We further find that this hybrid Ag@CNF-based nanocomposite shows a quick and low-voltage-triggered electrical-responsive shape memory behavior, making it a great candidate for printing electroactive devices. Multiple different as-printed Ag@CNF-based highly conductive nanocomposite structures used as high-performance electrical devices (e.g., ambient-printable conductive components, microstructured fiber sensors, flexible and lightweight scaffolds for electromagnetic interference shielding, and low-voltage-triggered smart grippers) are successfully demonstrated herein. This simple additive manufacturing approach combined with the synergic effects of the multimaterial nanocomposite paves new ways for further development of advanced and smart electrical devices in areas of soft robotics, sensors, wearable electronics, etc.

Noble-metal-coated carbon-based nanoparticles, when used as electrically conductive fillers, have the potential to provide excellent conductivity without the high weight and cost normally associated with metals such as silver and gold. To this effect, many attempts were made to deposit uniform metallic layers on core nanoparticles with an emphasis on silver for its high conductivity. The results so far were disheartening with the metal morphology being better described as a decoration than a coating with small effects on the electrical conductivity of the bulk particles. We tackled in this work the specific problem of electroless deposition of silver on carbon nanofibers (CNFs) with the investigation of every step of the process. We performed X-ray photoelectron spectroscopy (XPS), transmission and scanning electron microscopy (TEM, SEM), zeta potential, and electrical conductivity measurements to identify a repeatable, reliable set of parameters allowing for a uniform and fully connected silver deposition on the surface of the CNFs. The bulk particles' specific electrical conductivity (conductivity per unit mass) undergoes a more than 10-fold increase during the deposition, reaching 2500 S·cm/g, which indicates that the added metal mass participates efficiently to the conduction network. The particles keep their high aspect ratio through the process, which enables a percolated conduction network at very low volume loadings in a composite. No byproducts are produced during the reaction so the particles do not have to be sorted or purified and can be used as produced after the short ∼15 min reaction time. The particles might be an interesting replacement to conventional fillers in isotropic conductive adhesives, as a conductive network is obtained at a much lower loading. They might also serve as electrically conductive fillers in composites where a high conductivity is needed, such as lightning strike protection systems, or as high surface area silver electrodes.

UTBOX25 substrates are now ready for high volume manufacturing, as first substrate of choice for planar Fully- Depleted technology. Smart CutTM technology demonstrates its capability to provide ultra thin SOI & BOX layers with extremely tight thickness control as low as ± 5 Aå. Substrates to support scaling down to 11 nm node, including strained SOI, are under development and first results are presented

The Ultra-Thin SOI and BOX substrates are the foundation of Fully Depleted planar technology, a CMOS scaling solution for 20 nm node and beyond. Using the Smart CutTM technology, UTSOI substrates development, with SOI & BOX thickness reduced down to 12 & 25 nm respectively, is on the way to High Volume Manufacturing by the end of 2011. To improve device Vt variation control, SOI total layer thickness variation of less than +/- 1 nm for all the measured points and all the preproduction wafers is already achieved and +/- 0.5 nm variation is targeted. Tight SOI thickness variation at device scale and BOX thickness variation are also demonstrated.

Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCut TM technology which already allows achieving a maximum total SOI layer thickness variation of less than  10 Å on preproduction volume. Total thickness variation of  5 Å is targeted. SUBSTRATE REQUIREMENT FOR NEXT TECHNOLOGY NODESFor the future 20nm node, standard bulk CMOS technology is facing critical tradeoffs due to increasing random dopant fluctuation, i.e. increasing threshold voltage V T statistical variability. There is consensus in the IC industry that fully depleted (FD) devices with undoped channel, also known as Ultra Thin Body (UTB) devices [1], are effective solution for eliminating random dopant fluctuation (RDF) in the MOSFET channel, thus significantly reducing threshold voltage V T variability by over 60% [2].The foundation of the FD technology is the Ultra Thin SOI (UTSOI) substrate. The starting ultra thin Si thickness (UTSOI) has to be matched to the subsequent FD CMOS processing. Clean, oxidation and etch remove few Si monolayers and it has to be taken into account when specifying the initial UTSOI thickness. The targeted channel Si thickness is typically between 6nm -7nm for 25nm gate length transistor [2]. The starting UTSOI wafers exhibit SOI layer down to 10 nm and buried oxide layer from 145nm down to 10 nm.For FD devices the total random V T variability is the result of gate line edge roughness (LER), workfunction variability and of the channel Si thickness. Since the channel is undoped, there is no significant RDF contribution to V T variability.Thus, the thickness uniformity is a key parameter to avoid additional V T variation of the planar FDSOI device. Typical uniformity requirements include on-wafer uniformity and wafer-towafer uniformity. Both of them combined are classified as layer total thickness variation (LTTV) and define the overall manufacturing process window for thickness uniformity. LTTV has to be achieved at the sub-nanometer range for the UTSOI layer for all wafers and all sites in order to meet the FD specifications. UTSOI substrates target high volume production by second half of 2011 to enable the readiness of a 20nm FD CMOS technology platform. THICKNESS CONTROL REQUIREMENTKakhifirooz et al, have shown an empirical correspondence between V T variation on FD-SOI devices and SOI layer thickness variations. [3,4] From circuit and device considerations the maximum T Si fluctuation that can be tolerated is < 1nm within-wafer (WiW), total wafer range of the T Si non uniformity, and wafer-to-wafer (WtW), T Si reproducibility. This translates in a SOI T Si thickness maximum wafer-to-wafer variation of 5 Å.