We report on transport measurements of an InAs nanowire coupled to niobium nitride leads at high magnetic fields. We observe a zero-bias anomaly (ZBA) in the differential conductance of the nanowire for certain ranges of magnetic field and chemical potential. The ZBA can oscillate in width with either the magnetic field or chemical potential; it can even split and re-form. We discuss how our results relate to recent predictions of hybridizing Majorana fermions in semiconducting nanowires, while considering more mundane explanations.

A simple and effective method is presented for producing light-emitting porous silicon (PSi). A thin (d<10 nm) layer of Au, Pt, or Au/Pd is deposited on the (100) Si surface prior to immersion in a solution of HF and H2O2. Depending on the type of metal deposited and Si doping type and doping level, PSi with different morphologies and light-emitting properties is produced. PSi production occurs on the time scale of seconds, without electrical current, in the dark, on both p- and n-type Si. Thin metal coatings facilitate the etching in HF and H2O2, and of the metals investigated, Pt yields the fastest etch rates and produces PSi with the most intense luminescence. A reaction scheme involving local coupling of redox reactions with the metal is proposed to explain the metal-assisted etching process. The observation that some metal remains on the PSi surface after etching raises the possibility of fabricating in situ PSi contacts.

Soft errors are a growing concern for processor reliability. Recent work has motivated architecture-level studies of soft errors since the architecture can mask many raw errors and architectural solutions can exploit workload knowledge. This paper proposes a model and tool, called SoftArch, to enable analysis of soft errors at the architecturelevel in modern processors. SoftArch is based on a probabilistic model of the error generation and propagation process in a processor. Compared to prior architecture-level tools, SoftArch is more comprehensive or faster. We demonstrate the use of SoftArch for an out-of-order superscalar processor running SPEC2000 benchmarks. Our results are consistent with, but more comprehensive than, prior work, and motivate selective and dynamic architecture-level soft error protection mechanisms.

No abstract