To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45 nm technology. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by Science China Press and Springer-Verlag Berlin Heidelberg. 1 Fraunhofer IIS/EAS, Dresden D-010169,G e r m a n y 2 University of Freiburg, Freiburg D-79110,G e r m a n y 3 University of Paderborn, Paderborn D-33098,G e r m a n y 4 University of Passau, Passau D-94023,G e r m a n y 5 University of Stuttgart, Stuttgart D-70569,G e r m a n y Received March 21, 2011; accepted June 21, 2011Abstract To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level i...
The integration of sensors and actuators with microelectronics into either compact packages or onto a single silicon die is likely to be of major technological importance over the next decade. These systems are referred to as Microsystems or Micro-Electro-MechanicalSystems (MEMS). One obstacle to mass-market introduction are difficulties with quality and reliability verification. This paper outlines the difficulties of testing microsystems, shows approaches of test generation and verification transferable from the mixed-signal Integrated-Circuit (IC) domain, and demonstrates an on-line test designed for bridge-type, micromachined accelerometer and pressure sensors [1].
Through-silicon vias (TSVs) present new, essential elements within 3D stacked Integrated Circuits (IC). Since they connect different layers of 3D stacks, their proper operation is an essential prerequisite for the system function. In this paper a procedure for deriving local digital test sequences for TSVs is presented. The behavior of TSVs including their typical surrounding circuitry is investigated under the impact of assumed faults using fault simulation. Since a purely digital consideration of faulty behavior of TSVs is not sufficient, the TSVs have to be modeled and analyzed at electrical level. The TSVs are embedded by inverters used as drivers at the inputs and buffers at the outputs. All mentioned elements are described at electrical level by spice-like netlists. By an analogue fault simulation tool faults are injected into this electric network model. The simulations of the so modified networks were running in parallel on a compute cluster including the evaluations of the fault effects. The fault simulations are carried out automatically. The test signals needed for fault detection are concatenated to form a digital TSV test sequence
To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45 nm technology. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by Science China Press and Springer-Verlag Berlin Heidelberg. Fraunhofer IIS/EAS, Dresden D-010169,G e r m a n y 2 University of Freiburg, Freiburg D-79110,G e r m a n y 3 University of Paderborn, Paderborn D-33098,G e r m a n y 4 University of Passau, Passau D-94023,G e r m a n y 5 University of Stuttgart, Stuttgart D-70569,G e r m a n y Received March 21, 2011; accepted June 21, 2011Abstract To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level inf...
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