We propose improving system availability by performing in-field repair at the chip level. This enables margining and detection of degrading memory cells before the user observes any errors. A 576 Mb embedded DRAM at 1.5 GHz in a 40nm CMOS technology achieves improved resilience to both aging memory cells and cells with variable retention time (VRT). Un-interrupted user access of 6 billion 72-bit read and write operations per second is maintained during background repair.
IntroductionThe common approach to memory faults is to 1) in manufacturing detect and repair hard faults with column, row, and/or block redundancy and 2) in the field to detect and correct soft errors with error correcting codes (ECC) and background scrubbing. However, studies on DRAMs in high performance computing clusters [1] and Google's servers [2] have concluded that memory errors in the field are dominated by hard faults, which cannot be fixed by scrubbing.One limitation with scrubbing, system-level solutions such as mapping out persistent errors or de-allocating substantial address ranges, and the proposed in-field architectures to date [3,4] is that they do not detect faults before errors occur. Even if the system is able to recover when an error is encountered, the error handling may cause additional latency that may not be acceptable.In the following, we first present a study of aging and VRT memory bits. We show that aging bits can change gradually. We then describe an architecture and an implementation that take advantage of this phenomenon to detect and repair weak bits in the background without affecting user access or requiring system level error handling.
This paper reports on measurements of freestream nitric oxide (NO) rotational and vibrational temperatures and partial pressures, collected in the Caltech T5 reflected shock tunnel. Quantum cascade lasers, emitting mid-infrared light resonant with fundamental rovibrational NO transitions, were directed through the supersonic (Mach ∼5) freestream flow. Tunable diode laser absorption spectroscopy (TDLAS) was used to measure the path-averaged rotational and vibrational temperatures of NO in the flow, in addition to the NO partial pressure. The temperature measurements demonstrate strong evidence of NO rotational and vibrational equilibrium during the 1 ms test period. Agreement between vibrational and rotational temperatures was observed in all experiments, including one h 0;∞ ≈ 8 MJ∕kg and four h 0;∞ 18 MJ∕kg experiments, during and after the nominal test time. Absorption from CO and H 2 O was also observed in the TDLAS measurements, though their concentrations cannot be accurately estimated. The goal of these and future experiments is to develop and demonstrate TDLAS experimental strategies for high-enthalpy impulse facilities and to help to inform improvements of existing models and solvers used for prediction of freestream conditions.
As the demand for greater speed in semiconductor devices continues, a typical method of increasing charge mobility is to maximise the silicon strain at the depletion region in p-type transistors through the implementation of “Sigma Cavity” structures in the bulk silicon on either side of the gate structure. These structures, when filled, exhibit a uniaxial strain in the depletion region thus, increasing the charge transport speed [1]. The shape of the Sigma Cavity structure is important in maximising the strain in this region, thus strict control of the shape dimensions is imperative to the electrical performance of the device.
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