A ternary memristor full adder is designed based on the literal operation and module‐3 plus operation. Literal operation and module‐3 plus operation are the important operations in the tri‐valued algebra system. Multiple‐valued logic can increase the amount of information carried by the signals and reduce the number of devices and connections. The combination of multiple‐valued logic and memristor is an exploration of new devices and new structures. The novel ternary memristor full adder owns the advantage of simpler structure without decoding units to convert ternary signals to binary at the terminals, and all the signals operated by the circuit are ternary. Compared with the traditional ternary full adder, the number of devices and the power consumption are greatly reduced. Simulation results of different memristor models verified the correctness and applicability of the circuit design. It provides a new idea for the design method of memristor circuits, especially multiple‐valued memristors.
Due to the high manufacturing cost of memristors, an equivalent emulator has been employed as one of the mainstream approaches of memristor research. A threshold-type memristor emulator based on negative differential resistance (NDR) characteristics is proposed, with the core part being the R-HBT network composed of transistors. The advantage of the NDR-based memristor emulator is the controllable threshold, where the state of the memristor can be changed by setting the control voltage, which makes the memristor circuit design more flexible. The operation frequency of the memristor emulator is about 250 kHz. The experimental results prove the feasibility and correctness of the threshold-controllable memristor emulator circuit.
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