The gate charge change (ΔQg) of GaN-on-Si power devices subjected to different substrate biases has been investigated. On-wafer pulse-mode voltage stress measurement is examined to probe the physical insight of different trap mechanisms into Qg characteristics. Distinct injected electrons interacting with the buffer traps lead to a significant decrease (increase) in Qg under negative (positive) substrate bias. Different levels of degradation on ΔQgd to ΔQgs after stress under negative and positive substrate biases indicate uneven distribution of acceptor-like traps and uniform distribution of donor-like traps in the GaN buffer level. Using Arrhenius plots associated with the ΔQg shift, three dominant buffer traps with activation energies of EV + 0.542 eV, EC −0.604 eV, and EC −0.608 eV are extracted.
We report the growth of an ultrathin 1.0 nm ͑equivalent oxide thickness ϭ 0.86 nm) oxynitride gate dielectric by rapid thermal processing ͑RTP͒ in high-N 2 but low-O 2 gas flow ambient. The effect of the changing N 2 /O 2 gas flow ratio on the characteristics of oxynitride films was investigated. High-quality oxynitride film could be formed by RTP in an optimum N 2 /O 2 gas flow ratio of 5/1. Detailed characterization ͑transmission electron microscopy, J-E capacitance-voltage, stress-induced leakage current, charge-trapping properties͒ demonstrated the high quality of the oxynitride dielectric and showed that low leakage current density J g ϭ 0.1 A/cm 2 at 1 V, was 1.85 orders of magnitude lower than that of SiO 2 . These improvements are attributed to the presence of nitrogen at the interface and in the bulk of the oxynitride.Highly reliable and aggressively scaled gate dielectric films ͑equivalent oxide thickness, EOT р 1.0 nm) are necessary for developing complementary metal oxide semiconductor ͑CMOS͒ technologies in the sub-50 nm regime. However, when the thickness of SiO 2 is reduced below 2 nm, as for ultrathin oxides, important concerns of gate leakage and device reliability arise. 1-3 For these reasons, alternative gate dielectrics must be considered. In the course of searching for such an alternative gate dielectric, ultrathin NH 3 -nitride SiO 2 , N 2 O/NO oxynitride, N/O stack, plasma-nitrided SiO 2 , and high-k dielectrics have been widely studied as the promising replacements for thermal oxide as gate dielectrics, while maintaining a low gate leakage and increased capacitance for future sub-50 nm CMOS devices. 4-18 Desirable gate dielectrics should have good uniformity, small defect density, and high dielectric strength; they should endure hot-electron injection for maintaining device reliability. As mentioned above, much work in this field has been focused on the nitridation of SiO 2 . NH 3 -nitrided SiO 2 films can be effectively used to increase the proportion of incorporated N atoms; increasing the fixed charge and interface trap densities is unavoidable, due to the generation of electron traps related to -NH x , -H, and -OH bonds introduced from NH 3 . 4 The NH 3 -nitrided films have also been reported to show degraded mobility due to heavy nitridation and increased electron trapping. 5 N 2 O and NO have been proposed as alternatives without the disadvantages of NH 3 for oxidation and nitridation; the resulting films exhibit favorable electrical characteristics; however they do not have enough nitrogen ͑only ϳ1-2 atom %͒ at the dielectric silicon interface to prevent boron penetration. 6-9 The ultrathin nitride/oxide ͑N/O͒ stack has been investigated as a promising structure for suppressing leakage current and boron penetration, while maintaining the excellent oxide/Si interface. 10,11 The results of such investigations indicate that dielectric films formed by N/O stacks have higher nitrogen concentrations in both the bulk of the film and at the dielectric-silicon interface. However, most of the...
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