Experimental investigation of buffer traps physical mechanisms on the gate charge of GaN-on-Si devices under various substrate biases

Abstract

The gate charge change (ΔQg) of GaN-on-Si power devices subjected to different substrate biases has been investigated. On-wafer pulse-mode voltage stress measurement is examined to probe the physical insight of different trap mechanisms into Qg characteristics. Distinct injected electrons interacting with the buffer traps lead to a significant decrease (increase) in Qg under negative (positive) substrate bias. Different levels of degradation on ΔQgd to ΔQgs after stress under negative and positive substrate biases indicate uneven distribution of acceptor-like traps and uniform distribution of donor-like traps in the GaN buffer level. Using Arrhenius plots associated with the ΔQg shift, three dominant buffer traps with activation energies of EV + 0.542 eV, EC −0.604 eV, and EC −0.608 eV are extracted.

Effect of C- and Fe-doped GaN buffer on AlGaN/GaN high electron mobility transistor performance on GaN substrate using side-gate modulation

“…Similar mechanisms were reported in back-gate studies of C-doped GaN buffer. [38][39][40][41] This could explain the hysteresis behavior observed in Figs. 9 and 12.…”

“…One common way to characterize buffer layers is through back-gating measurements, where high voltages are applied to the substrate to probe the buffer layer. [36][37][38][39][40] The simplest version of this technique involves applying a high substrate biases (V SUB ) while the change in channel carrier density is monitored by the drain current (I D ). This is known to be an effective method in characterizing traps in the buffer layer.…”

“…This is known to be an effective method in characterizing traps in the buffer layer. 39,40) In an ideal trap-free buffer, there is linear relationship between the applied V SUB and channel current, however, if there are charged traps in the buffer, the field distribution for the same applied V SUB will be changed, and thus, affecting I D . 36,37,41) S. Yang et al reported that V SUB bias ramping with high positive and negative voltages can induce trapping/detrapping and charge redistribution in the buffer resulting to partially depleted 2DEG.…”

Characterization of AlGaN/GaN high electron mobility transistors on GaN substrates with different thicknesses of GaN channel and buffer layers using side-gate modulation

“…One effective method in characterizing traps in the buffer layer is through back-gating measurements. [33][34][35][36][37] In the simplest version of this technique, a high substrate bias (V SUB ) is applied at the back of the substrate while the change in the carrier density is monitored by the drain current (I D ). In contrast to the common back-gating method, side-gating approach was adopted in the present work where a separate side-gate (SG) contact is bias ramped instead of a back-gate contact.…”

Thermal effect on dynamic R_on degradation of p-GaN AlGaN/GaN HEMTs on SiC substrates

“…A p-type doped GaN layer is covered locally under the gate in order to achieve enough high threshold voltage with a low specific on-resistance [6,7,8,9,10]. However, the capabilities of a full integrated GaN power electronics are still limited by several reliability issues when GaN HEMTs are operated between kHz to MHz switching frequencies [11,12,13,14,15,16].…”