The design and physical implementation of an embedded memory utilising bit-area efficient hybrid gain cell is presented. The memory cells in this work are composed of a high-threshold NMOS write transistor and a standard-threshold NMOS read transistor. The bit data are stored on the parasitic capacitances within the cells. Owing to the combination of low subthreshold-leakage write device and high mobility read device, this NMOS-based hybrid 2T gain cell exhibits much improved data retention and read performance in a compact bit area. The memory arrays operate with a logic-compatible supply voltage; SRAM-like I/O interface; chip-select-controlled 128-row refresh; and non-destructive read with speed comparable with 6T SRAM, but 65% smaller cell area. Measurement results from a 32 kbit pseudo-SRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed embedded memory techniques.
A gain cell embedded dynamic random access memory (eDRAM) with a noble charge injection technique is presented. The gain memory cell is composed of dual-threshold two logic N-type MOSs implemented in a generic triple-well CMOS process. A negative-voltage toggle on the parasitic junction diode formed between the pocket p-well and the cell data node couples up the cell storage voltages. It results in a much enhanced retention time in a compact bit area. Moreover, the technique exhibits much strong immunity from the write disturbance. Measured results at 85°C from a 110 nm 64 kbit prototype eDRAM incorporating the proposed technique demonstrate 69% enhanced retention time and 86% smaller write disturbance loss compared with the conventional one.
Abstract:The design and physical implementation of a low-power SRAM with 4T CMOS latch bit-cell is presented. The memory cells in this work are composed of two cross-coupled inverters without any access transistors. They are accessed by totally novel read and write methods that result in low operating power dissipation in the nature. A 1.8 V SRAM test chip has been fabricated in a 0.18 μm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30% reduction in read power and 42% reduction in write power compared to the standard 6T SRAM.
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