Acute necrotizing encephalopathy (ANE) is a rare but distinctive type of acute encephalopathy with global distribution. Occurrence of ANE is usually preceded by a virus-associated febrile illness and ensued by rapid deterioration. However, the causal relationship between viral infections and ANE and the exact pathogenesis of ANE remain unclear; both environmental and host factors might be involved. Most cases of ANE are sporadic and nonrecurrent, namely, isolated or sporadic ANE; however, few cases are recurrent and with familial episodes. The recurrent and familial forms of ANE were found to be incompletely autosomal-dominant. Further the missense mutations in the gene encoding the nuclear pore protein Ran Binding Protein 2 (RANBP2) were identified. Although the clinical course and the prognosis of ANE are diverse, the hallmark of neuroradiologic manifestation of ANE is multifocal symmetric brain lesions which are demonstrated by computed tomography (CT) or magnetic resonance imaging (MRI). The treatment of ANE is still under investigation. We summarize the up-to-date knowledge on ANE, with emphasis on prompt diagnosis and better treatment of this rare but fatal disease.

Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically refreshed to retain data. Like SRAM, eDRAM is susceptible to device variations, which play a role in determining refresh time for eDRAM cells. Refresh power potentially represents a large fraction of overall system power, particularly during low-power states when the CPU is idle. Future designs need to reduce cache power without incurring the high cost of flushing cache data when entering low-power states.In this paper, we show the significant impact of variations on refresh time and cache power consumption for large eDRAM caches. We propose Hi-ECC, a technique that incorporates multibit error-correcting codes to significantly reduce refresh rate. Multi-bit error-correcting codes usually have a complex decoder design and high storage cost. Hi-ECC avoids the decoder complexity by using strong ECC codes to identify and disable sections of the cache with multi-bit failures, while providing efficient single-bit error correction for the common case. Hi-ECC includes additional optimizations that allow us to amortize the storage cost of the code over large data words, providing the benefit of multi-bit correction at same storage cost as a single-bit error-correcting (SECDED) code (2% overhead). Our proposal achieves a 93% reduction in refresh power vs. a baseline eDRAM cache without error correcting capability, and a 66% reduction in refresh power vs. a system using SECDED codes.

ABSTRACT

Voltage scaling is one of the most effective mechanisms to improve microprocessors" energy efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin, since hardware structures may fail. Cell failures in large memory arrays (e.g., caches) typically determine Vccmin for the whole processor. We observe that most cache lines exhibit zero or one failures at low voltages. However, a few lines, especially in large caches, exhibit multi-bit failures and increase Vccmin. Previous solutions either significantly reduce cache capacity to enable uniform error correction across all lines, or significantly increase latency and bandwidth overheads when amortizing the cost of error-correcting codes (ECC) over large lines.In this paper, we propose a novel cache architecture that uses variable-strength error-correcting codes (VS-ECC). In the common case, lines with zero or one failures use a simple and fast ECC. A small number of lines with multi-bit failures use a strong multi-bit ECC that requires some additional area and latency. We present a novel dynamic cache characterization mechanism to determine which lines will exhibit multi-bit failures. In particular, we use multi-bit correction to protect a fraction of the cache after switching to low voltage, while dynamically testing the remaining lines for multi-bit failures. Compared to prior multi-bit-correcting proposals, VS-ECC significantly reduces power and energy, avoids significant reductions in cache capacity, incurs little area overhead, and avoids large increases in latency and bandwidth.

Adipose-derived mesenchymal stem cells are available across all age groups. Infant-derived cells are morphologically spindle-shaped, with long telomeres, and exhibit enhanced angiogenic and osteogenic capabilities compared with older cells. Conversely, all age groups exhibit similar osteogenic paracrine activity, and the authors posit that clinical applicability is conserved during the adult to elderly period.