This paper direct to security and real-time requirements in high-speed network transmission processing, based on SOPC technology, design a High throughput AES encryption/ decryption processing unit with pipelining. The design goal is to optimize the hardware structure and improve the throughput, S-box design and parallel processing structure. Compared with traditional AES crypto-chip has faster rate with encryption and less consumption of resources advantages. This design adopts VHDL hardware description language, use Quartus II 8.0 for the synthesis and routing, and this processing unit is packaged an independent IP core, attached to the Altera provided the Nios II system, finally download and test validation on the DE2 development platform.
Encryption is the core of security technology. The paper managed to design and implement a kind of reconfigurable cipher unit based on the 3DES/AES and optimized by FPGA technology, which can effectively support diverse cryptographic algorithms and can meet the demand on system performance and flexibility. The unit uses hardware description language VHDL, layout and wire on QuartusII8.0. Finally the system is downloaded to DE2 for testing. The design hardware structure is simple, flexibility, security, which can be widely used in the field of information security.
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