The Design and Implementation of a High-Speed Parallel AES Crypto-Chip

Abstract

This paper direct to security and real-time requirements in high-speed network transmission processing, based on SOPC technology, design a High throughput AES encryption/ decryption processing unit with pipelining. The design goal is to optimize the hardware structure and improve the throughput, S-box design and parallel processing structure. Compared with traditional AES crypto-chip has faster rate with encryption and less consumption of resources advantages. This design adopts VHDL hardware description language, use Quartus II 8.0 for the synthesis and routing, and this processing unit is packaged an independent IP core, attached to the Altera provided the Nios II system, finally download and test validation on the DE2 development platform.

The Design and Implementation of Reconfigurable Cipher Unit on FPGA

“…Encryption process include byte substitution transformation, line shift change, column mixing transformation and different round keys or change, after Nr iteration, of which final round not do column mixing transformation. Decryption process is similar to the encryption process, all aspects of use the inverse transformation [4]. Encryption and decryption algorithms used in the same sub-key, each round require the participation of an extended key which is the same length as input packets, but the order is opposite.…”