To track the desired pose of the omnidirectional autonomous mobile robot (OAMR) in finite time, the finite-time virtual desired trajectory (FTVDT) is designed by the 1st sliding surface with the linear dynamics and fractional order of pose's tracking error. To track the FTVDT in finite time, the finite-time sliding-mode saturated control (FTSMSC) is designed by the second sliding surface with the linear dynamics and fractional order of the FTVDT's tracking error. In short, the proposed hierarchical finite-time slidingmode control with input saturation (HFTSMCIS) contains the FTVDT and the FTSMSC. As compared with previous studies, the finite-time trajectory tracking with the reduced chattering control input is achieved by the suitable selection of control parameters. The HFTSMCIS algorithm is executed in the CPU, and then it is transformed to a PWM signal using FPGA hardware and the motor velocity is simultaneously decoded by the FPGA hardware for feedback control. In contrast, the other state signals are achieved from the mathematical model such that the feedback control system is simple and effective. It is so-called software/hardwarebased HFTSMCIS (SHB-HFTSMCIS). Finally, three experiments, including two different process time and obstacle avoidance, are presented to validate the effectiveness and robustness of the proposed control system.
Network-on-Chip (NoC) has been proposed to overcome the complex on-chip communication problem of SoC (Systemon-Chip) design in deep submicron. A complete NoC design contains exploration on both hardware and software architectures. The hardware architecture includes the selection of PEs (Processing Elements) with multiple types and their topology. The software architecture contains the allocation of tasks to PEs, scheduling of tasks and their communications. To find the best hardware design for the target tasks, both hardware and software architectures need to be considered simultaneously. Previous works on NoC design have concentrated on solving for only one or two design parameters at a time. In this paper, we propose a hardware-software co-synthesis algorithm for a heterogeneous NoC architecture. The design goal is to minimize energy consumption while meeting the real-time requirements commonly seen in the embedded applications.
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