In this paper, we propose a rateless, three-stage, two-way multiply-and-forward (MF) relaying system over the Rayleigh flat fading channel, where two source nodes communicate with each other through a relay node and all nodes work on half-duplex and time-division mode. We thoroughly analyze the signals during all three stages in the proposed MF system and derive the closed-form symbol error rate (SER) expressions for an uncoded MF-two-way relay network (MF-TWRN). Furthermore, we provide the equivalent point-to-point fading channel model, which is employed to carry out the asymptotic performance analysis. We finally put forth an optimization model for the MF-TWRN with fountain codes. Simulation results show that our optimized degree distribution can provide outstanding performance for the MF-TWRN compared to those in the literature.
This paper proposes a design and realization of a network security system based on unidirectional network data control technique and configurable Rijndael AES algorithm.The unidirectional control technique does not process the data downloaded from the server to the client side but checks the data that is uploaded to the server side according to certain security rules, which promises the client side can receive complete and real-time data flow from the server side and prevents key information in private network from being disclosed. Moreover, using the improved AES data encryption standard, messages within the private network are encrypted, which promises the information could be transmitted in security even it is eavesdropped.
This paper presents an approach of Time-Triggered Ethernet (TTEthernet, TTE) clock synchronization. Firstly it introduces the roles of each device in clock synchronization algorithm, then analysizes the synchronization steps and their two sub-algorithms:permanencealgorithm andcompressedalgorithm. At last it presents the process of clock correction in different devices.
Imported clock synchronization and time-triggered strategy in standard Ethernet, Time-Triggered Ethernet has its unique features. This paper introduces its traffic features, clock synchronization, standard configuration and scheduling strategy. Due to its new features Time-triggered Ethernet will have completely new application areas.
In recent years, with the development of microelectronics technology, microsystems based on SIP/SoC have been applied to drone and other avionics systems. It is practical to study the reconfigurable calculation of avionics microsystems facing the flexible use of the scene. Encryption/decryption data based on FPGA can adapt to different application environments and functional requirements, which is especially important for product protection. However, implementing multiple algorithms on the same chip leads to increased logic resource consumption, low resource utilization, and poor system flexibility. In view of the above problems, it is necessary to design a dynamic reconfigurable computing platform based on an aviation SIP micro-system chip with dynamic reconfigurable technology as the core (using Zynq SoC). The platform use on-chip ARM processor to control reconfiguration. The different encryption and decryption algorithm logics are configured into different logical partitions on the chip according to the requirement. The logic circuit is updated and the algorithm is reconstructed. Different encryption and decryption algorithms are implemented by using the HLS method. The verification results show that the design can complete the algorithm switching at a higher configuration speed while the other functions on the chip work normally. Under the premise of ensuring the stability of the system, the on-chip logic resource consumption is reduced, and the resource utilization and system flexibility are improved.
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