Introduction:We report measurements of the DC characteristics of sub-l00nm nMOSFETs that employ low leakage. ultra-thin gate oxides only 1 -2nm thick to achieve high current drive capability and transconductance. We demonstrate that ZDsctr=: 1.8mAIp.m can be achieved with a 60nm gate at 1.5V using a 1.3-1.4nm gate oxide with a gate leakage current less than 20r~AIp.m~. Furthermore, we find that ZDscrr deteriorates for gate oxides thicker or thinner than this.Fabrication: We have explored a gate stack consisting of l00nm of TEOS hard mask over 80nm of doped W.5, on 1 00nm of in-situ phosphorus-doped poly-crystalline silicon on gate oxides ranging in thickness from 1 -2nm thick on a ptype epitaxial silicon. Prior to the oxide growth, the substrates were stripped by immersion into a 15: 1 H 2 0: HF solution for only 5 seconds (to minimize surface roughness and pitting) and then subjected to a vapor phase clean in 10 Torr
Abstract-Intelligent systems like automatic highway traffic management, area surveillance, and geological activity monitoring require substantial data collection and processing in the field. Energy self-sustainability is a critical foundation for successful field systems that are away from the power grid infrastructure. Instead of the conventional battery-based energy storage, this paper argues that the super capacitor buffering of solar energy (SOLARCAP) has the advantages of precise energy lifetime awareness, low maintenance, and operational robustness. By designing and developing a prototype implementation of the circuitry required for management and harvesting of energy, we demonstrate a SOLARCAP system that ensures safe device operation within the permitted voltage range.
We have demonstrated that the threshold voltage shifts in closely spaced, dual-poly CMOS devices are virtually eliminated by using buried, low energy gate implants. The reduced thermal budget lor gate activation, made possible by short dillusion distances, not only reduces dopant lateral diffusion in the gates but also in the device channel regions. Moreover, the process allows the use of thinner gate oxides and shallower junctions and improves the control of LM. IntroductionRecent advances in CMOS device isolation schemes make possible greatly increased device packing density. However, aggressive scaling of the PTOX-NTOX separation to submicron regime (0.4-0.6pn for 0.18pm CMOS) makes closely spaced P-and NMOS dual-poly devices with connected gates susceptible to cross-doping ellects, irrespective of the choice of the gate metal. Ai these dimensions, the device characteristics can be adversely affected by dopant lateral dillusion not only in the gate metal but also in the polysilicon layer itsell. In this work, we describe a novel processing scheme that ensures that dopant diffusion distances during gate drive-in and activation are much shorter than distanceshes needed lor dopant cross-diffusion, The gate structures are based on the concept of buried, ultra-low energy gate implants, utilizing the new generation of highcurrent, low energy ion implanters that have only recently become available 11).
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